spear-shirq.c (9fc0fd6b052be4390138bb6c4bae07d6b7e1aa66) spear-shirq.c (da89947b47a3a355f33a75d7672892c147ed880d)
1/*
2 * SPEAr platform shared irq layer source file
3 *
4 * Copyright (C) 2009-2012 ST Microelectronics
1/*
2 * SPEAr platform shared irq layer source file
3 *
4 * Copyright (C) 2009-2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com>
5 * Viresh Kumar <vireshk@kernel.org>
6 *
7 * Copyright (C) 2012 ST Microelectronics
8 * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16#include <linux/err.h>
17#include <linux/export.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/irq.h>
6 *
7 * Copyright (C) 2012 ST Microelectronics
8 * Shiraz Hashim <shiraz.linux.kernel@gmail.com>
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15
16#include <linux/err.h>
17#include <linux/export.h>
18#include <linux/interrupt.h>
19#include <linux/io.h>
20#include <linux/irq.h>
21#include <linux/irqchip.h>
22#include <linux/irqdomain.h>
23#include <linux/of.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
26#include <linux/spinlock.h>
27
21#include <linux/irqdomain.h>
22#include <linux/of.h>
23#include <linux/of_address.h>
24#include <linux/of_irq.h>
25#include <linux/spinlock.h>
26
27#include "irqchip.h"
28
28/*
29 * struct spear_shirq: shared irq structure
30 *
31 * base: Base register address
32 * status_reg: Status register offset for chained interrupt handler
33 * mask_reg: Mask register offset for irq chip
34 * mask: Mask to apply to the status register
35 * virq_base: Base virtual interrupt number

--- 141 unchanged lines hidden (view full) ---

177
178static struct spear_shirq *spear320_shirq_blocks[] = {
179 &spear320_shirq_ras3,
180 &spear320_shirq_ras1,
181 &spear320_shirq_ras2,
182 &spear320_shirq_intrcomm_ras,
183};
184
29/*
30 * struct spear_shirq: shared irq structure
31 *
32 * base: Base register address
33 * status_reg: Status register offset for chained interrupt handler
34 * mask_reg: Mask register offset for irq chip
35 * mask: Mask to apply to the status register
36 * virq_base: Base virtual interrupt number

--- 141 unchanged lines hidden (view full) ---

178
179static struct spear_shirq *spear320_shirq_blocks[] = {
180 &spear320_shirq_ras3,
181 &spear320_shirq_ras1,
182 &spear320_shirq_ras2,
183 &spear320_shirq_intrcomm_ras,
184};
185
185static void shirq_handler(unsigned __irq, struct irq_desc *desc)
186static void shirq_handler(unsigned irq, struct irq_desc *desc)
186{
187{
187 struct spear_shirq *shirq = irq_desc_get_handler_data(desc);
188 struct spear_shirq *shirq = irq_get_handler_data(irq);
188 u32 pend;
189
190 pend = readl(shirq->base + shirq->status_reg) & shirq->mask;
191 pend >>= shirq->offset;
192
193 while (pend) {
194 int irq = __ffs(pend);
195

--- 94 unchanged lines hidden --- 		189 u32 pend;
190
191 pend = readl(shirq->base + shirq->status_reg) & shirq->mask;
192 pend >>= shirq->offset;
193
194 while (pend) {
195 int irq = __ffs(pend);
196

--- 94 unchanged lines hidden ---