qcom-pdc.c (d494d088ac44b9cf561362a7856fa20b656be64f) qcom-pdc.c (a6aca2f460e203781dc41391913cc5b54f4bc0ce)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/err.h>
7#include <linux/init.h>
8#include <linux/interrupt.h>

--- 41 unchanged lines hidden (view full) ---

50static u32 pdc_reg_read(int reg, u32 i)
51{
52 return readl_relaxed(pdc_base + reg + i * sizeof(u32));
53}
54
55static void pdc_enable_intr(struct irq_data *d, bool on)
56{
57 int pin_out = d->hwirq;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/err.h>
7#include <linux/init.h>
8#include <linux/interrupt.h>

--- 41 unchanged lines hidden (view full) ---

50static u32 pdc_reg_read(int reg, u32 i)
51{
52 return readl_relaxed(pdc_base + reg + i * sizeof(u32));
53}
54
55static void pdc_enable_intr(struct irq_data *d, bool on)
56{
57 int pin_out = d->hwirq;
58 unsigned long flags;
58 u32 index, mask;
59 u32 enable;
60
61 index = pin_out / 32;
62 mask = pin_out % 32;
63
59 u32 index, mask;
60 u32 enable;
61
62 index = pin_out / 32;
63 mask = pin_out % 32;
64
64 raw_spin_lock(&pdc_lock);
65 raw_spin_lock_irqsave(&pdc_lock, flags);
65 enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
66 enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
67 pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
66 enable = pdc_reg_read(IRQ_ENABLE_BANK, index);
67 enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);
68 pdc_reg_write(IRQ_ENABLE_BANK, index, enable);
68 raw_spin_unlock(&pdc_lock);
69 raw_spin_unlock_irqrestore(&pdc_lock, flags);
69}
70
71static void qcom_pdc_gic_disable(struct irq_data *d)
72{
73 pdc_enable_intr(d, false);
74 irq_chip_disable_parent(d);
75}
76

--- 267 unchanged lines hidden --- 		70}
71
72static void qcom_pdc_gic_disable(struct irq_data *d)
73{
74 pdc_enable_intr(d, false);
75 irq_chip_disable_parent(d);
76}
77

--- 267 unchanged lines hidden ---