irq-hip04.c (9095bf25ea08135a5b74875dd0e3eeaddc4218a0) irq-hip04.c (79a0d4d8f1ae9568a952c8e5928ee81b30c8df11)
1/*
2 * Hisilicon HiP04 INTC
3 *
4 * Copyright (C) 2002-2014 ARM Limited.
5 * Copyright (c) 2013-2014 Hisilicon Ltd.
6 * Copyright (c) 2013-2014 Linaro Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify

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160 raw_spin_lock(&irq_controller_lock);
161 reg = hip04_dist_base(d) + GIC_DIST_TARGET + ((hip04_irq(d) * 2) & ~3);
162 mask = 0xffff << shift;
163 bit = hip04_cpu_map[cpu] << shift;
164 val = readl_relaxed(reg) & ~mask;
165 writel_relaxed(val | bit, reg);
166 raw_spin_unlock(&irq_controller_lock);
167
1/*
2 * Hisilicon HiP04 INTC
3 *
4 * Copyright (C) 2002-2014 ARM Limited.
5 * Copyright (c) 2013-2014 Hisilicon Ltd.
6 * Copyright (c) 2013-2014 Linaro Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify

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160 raw_spin_lock(&irq_controller_lock);
161 reg = hip04_dist_base(d) + GIC_DIST_TARGET + ((hip04_irq(d) * 2) & ~3);
162 mask = 0xffff << shift;
163 bit = hip04_cpu_map[cpu] << shift;
164 val = readl_relaxed(reg) & ~mask;
165 writel_relaxed(val | bit, reg);
166 raw_spin_unlock(&irq_controller_lock);
167
168 irq_data_update_effective_affinity(d, cpumask_of(cpu));
169
168 return IRQ_SET_MASK_OK;
169}
170#endif
171
172static void __exception_irq_entry hip04_handle_irq(struct pt_regs *regs)
173{
174 u32 irqstat, irqnr;
175 void __iomem *cpu_base = hip04_data.cpu_base;

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307 irq_set_percpu_devid(irq);
308 irq_set_chip_and_handler(irq, &hip04_irq_chip,
309 handle_percpu_devid_irq);
310 irq_set_status_flags(irq, IRQ_NOAUTOEN);
311 } else {
312 irq_set_chip_and_handler(irq, &hip04_irq_chip,
313 handle_fasteoi_irq);
314 irq_set_probe(irq);
170 return IRQ_SET_MASK_OK;
171}
172#endif
173
174static void __exception_irq_entry hip04_handle_irq(struct pt_regs *regs)
175{
176 u32 irqstat, irqnr;
177 void __iomem *cpu_base = hip04_data.cpu_base;

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309 irq_set_percpu_devid(irq);
310 irq_set_chip_and_handler(irq, &hip04_irq_chip,
311 handle_percpu_devid_irq);
312 irq_set_status_flags(irq, IRQ_NOAUTOEN);
313 } else {
314 irq_set_chip_and_handler(irq, &hip04_irq_chip,
315 handle_fasteoi_irq);
316 irq_set_probe(irq);
317 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq)));
315 }
316 irq_set_chip_data(irq, d->host_data);
317 return 0;
318}
319
320static int hip04_irq_domain_xlate(struct irq_domain *d,
321 struct device_node *controller,
322 const u32 *intspec, unsigned int intsize,

--- 92 unchanged lines hidden --- 		318 }
319 irq_set_chip_data(irq, d->host_data);
320 return 0;
321}
322
323static int hip04_irq_domain_xlate(struct irq_domain *d,
324 struct device_node *controller,
325 const u32 *intspec, unsigned int intsize,

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