iommu.h (06c375053cefc3a2f383d200596abe5ab3fb35f9) iommu.h (621b7e54f288c5e4e32d1dd81a926b8ecb547c60)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright © 2006-2015, Intel Corporation.
4 *
5 * Authors: Ashok Raj <ashok.raj@intel.com>
6 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
7 * David Woodhouse <David.Woodhouse@intel.com>
8 */

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450#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
451#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
452#define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
453 ((u64)((pfsid >> 4) & 0xfff) << 52))
454#define QI_DEV_EIOTLB_MAX_INVS 32
455
456/* Page group response descriptor QW0 */
457#define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright © 2006-2015, Intel Corporation.
4 *
5 * Authors: Ashok Raj <ashok.raj@intel.com>
6 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
7 * David Woodhouse <David.Woodhouse@intel.com>
8 */

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450#define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
451#define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
452#define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
453 ((u64)((pfsid >> 4) & 0xfff) << 52))
454#define QI_DEV_EIOTLB_MAX_INVS 32
455
456/* Page group response descriptor QW0 */
457#define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
458#define QI_PGRP_PDP(p) (((u64)(p)) << 5)
459#define QI_PGRP_RESP_CODE(res) (((u64)(res)) << 12)
460#define QI_PGRP_DID(rid) (((u64)(rid)) << 16)
461#define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
462
463/* Page group response descriptor QW1 */
464#define QI_PGRP_LPIG(x) (((u64)(x)) << 2)
465#define QI_PGRP_IDX(idx) (((u64)(idx)) << 3)
466

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1080void domain_detach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu);
1081void device_block_translation(struct device *dev);
1082int prepare_domain_attach_device(struct iommu_domain *domain,
1083 struct device *dev);
1084void domain_update_iommu_cap(struct dmar_domain *domain);
1085
1086int dmar_ir_support(void);
1087
458#define QI_PGRP_RESP_CODE(res) (((u64)(res)) << 12)
459#define QI_PGRP_DID(rid) (((u64)(rid)) << 16)
460#define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
461
462/* Page group response descriptor QW1 */
463#define QI_PGRP_LPIG(x) (((u64)(x)) << 2)
464#define QI_PGRP_IDX(idx) (((u64)(idx)) << 3)
465

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1079void domain_detach_iommu(struct dmar_domain *domain, struct intel_iommu *iommu);
1080void device_block_translation(struct device *dev);
1081int prepare_domain_attach_device(struct iommu_domain *domain,
1082 struct device *dev);
1083void domain_update_iommu_cap(struct dmar_domain *domain);
1084
1085int dmar_ir_support(void);
1086
1087void *alloc_pgtable_page(int node, gfp_t gfp);
1088void free_pgtable_page(void *vaddr);
1088void iommu_flush_write_buffer(struct intel_iommu *iommu);
1089struct iommu_domain *intel_nested_domain_alloc(struct iommu_domain *parent,
1090 const struct iommu_user_data *user_data);
1091struct device *device_rbtree_find(struct intel_iommu *iommu, u16 rid);
1092
1093#ifdef CONFIG_INTEL_IOMMU_SVM
1094void intel_svm_check(struct intel_iommu *iommu);
1095int intel_svm_enable_prq(struct intel_iommu *iommu);

--- 112 unchanged lines hidden --- 		1089void iommu_flush_write_buffer(struct intel_iommu *iommu);
1090struct iommu_domain *intel_nested_domain_alloc(struct iommu_domain *parent,
1091 const struct iommu_user_data *user_data);
1092struct device *device_rbtree_find(struct intel_iommu *iommu, u16 rid);
1093
1094#ifdef CONFIG_INTEL_IOMMU_SVM
1095void intel_svm_check(struct intel_iommu *iommu);
1096int intel_svm_enable_prq(struct intel_iommu *iommu);

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