sm8450.c (be02db24cf840bc0fdfbecc78ad803619dd143e6) sm8450.c (cff66ace51e3acfcba3ab03f92adc9510830c365)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, Linaro Limited
5 */
6
7#include <linux/device.h>
8#include <linux/interconnect.h>
9#include <linux/interconnect-provider.h>
10#include <linux/module.h>
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021, Linaro Limited
5 */
6
7#include <linux/device.h>
8#include <linux/interconnect.h>
9#include <linux/interconnect-provider.h>
10#include <linux/module.h>
11#include <linux/of_platform.h>
11#include <linux/mod_devicetable.h>
12#include <linux/platform_device.h>
13#include <linux/property.h>
12#include <dt-bindings/interconnect/qcom,sm8450.h>
13
14#include "bcm-voter.h"
15#include "icc-common.h"
16#include "icc-rpmh.h"
17#include "sm8450.h"
18
19static struct qcom_icc_node qhm_qspi = {

--- 1312 unchanged lines hidden (view full) ---

1332 .channels = 2,
1333 .buswidth = 32,
1334 .num_links = 1,
1335 .links = { SM8450_MASTER_MNOC_SF_MEM_NOC_DISP },
1336};
1337
1338static struct qcom_icc_bcm bcm_acv = {
1339 .name = "ACV",
14#include <dt-bindings/interconnect/qcom,sm8450.h>
15
16#include "bcm-voter.h"
17#include "icc-common.h"
18#include "icc-rpmh.h"
19#include "sm8450.h"
20
21static struct qcom_icc_node qhm_qspi = {

--- 1312 unchanged lines hidden (view full) ---

1334 .channels = 2,
1335 .buswidth = 32,
1336 .num_links = 1,
1337 .links = { SM8450_MASTER_MNOC_SF_MEM_NOC_DISP },
1338};
1339
1340static struct qcom_icc_bcm bcm_acv = {
1341 .name = "ACV",
1340 .enable_mask = 0x8,
1341 .num_nodes = 1,
1342 .nodes = { &ebi },
1343};
1344
1345static struct qcom_icc_bcm bcm_ce0 = {
1346 .name = "CE0",
1347 .num_nodes = 1,
1348 .nodes = { &qxm_crypto },
1349};
1350
1351static struct qcom_icc_bcm bcm_cn0 = {
1352 .name = "CN0",
1342 .num_nodes = 1,
1343 .nodes = { &ebi },
1344};
1345
1346static struct qcom_icc_bcm bcm_ce0 = {
1347 .name = "CE0",
1348 .num_nodes = 1,
1349 .nodes = { &qxm_crypto },
1350};
1351
1352static struct qcom_icc_bcm bcm_cn0 = {
1353 .name = "CN0",
1353 .enable_mask = 0x1,
1354 .keepalive = true,
1355 .num_nodes = 55,
1356 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
1357 &qhs_ahb2phy0, &qhs_ahb2phy1,
1358 &qhs_aoss, &qhs_camera_cfg,
1359 &qhs_clk_ctl, &qhs_compute_cfg,
1360 &qhs_cpr_cx, &qhs_cpr_mmcx,
1361 &qhs_cpr_mxa, &qhs_cpr_mxc,

--- 18 unchanged lines hidden (view full) ---

1380 &qxs_imem, &qxs_pimem,
1381 &srvc_cnoc, &xs_pcie_0,
1382 &xs_pcie_1, &xs_qdss_stm,
1383 &xs_sys_tcu_cfg },
1384};
1385
1386static struct qcom_icc_bcm bcm_co0 = {
1387 .name = "CO0",
1354 .keepalive = true,
1355 .num_nodes = 55,
1356 .nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie,
1357 &qhs_ahb2phy0, &qhs_ahb2phy1,
1358 &qhs_aoss, &qhs_camera_cfg,
1359 &qhs_clk_ctl, &qhs_compute_cfg,
1360 &qhs_cpr_cx, &qhs_cpr_mmcx,
1361 &qhs_cpr_mxa, &qhs_cpr_mxc,

--- 18 unchanged lines hidden (view full) ---

1380 &qxs_imem, &qxs_pimem,
1381 &srvc_cnoc, &xs_pcie_0,
1382 &xs_pcie_1, &xs_qdss_stm,
1383 &xs_sys_tcu_cfg },
1384};
1385
1386static struct qcom_icc_bcm bcm_co0 = {
1387 .name = "CO0",
1388 .enable_mask = 0x1,
1389 .num_nodes = 2,
1390 .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1391};
1392
1393static struct qcom_icc_bcm bcm_mc0 = {
1394 .name = "MC0",
1395 .keepalive = true,
1396 .num_nodes = 1,

--- 4 unchanged lines hidden (view full) ---

1401 .name = "MM0",
1402 .keepalive = true,
1403 .num_nodes = 1,
1404 .nodes = { &qns_mem_noc_hf },
1405};
1406
1407static struct qcom_icc_bcm bcm_mm1 = {
1408 .name = "MM1",
1388 .num_nodes = 2,
1389 .nodes = { &qxm_nsp, &qns_nsp_gemnoc },
1390};
1391
1392static struct qcom_icc_bcm bcm_mc0 = {
1393 .name = "MC0",
1394 .keepalive = true,
1395 .num_nodes = 1,

--- 4 unchanged lines hidden (view full) ---

1400 .name = "MM0",
1401 .keepalive = true,
1402 .num_nodes = 1,
1403 .nodes = { &qns_mem_noc_hf },
1404};
1405
1406static struct qcom_icc_bcm bcm_mm1 = {
1407 .name = "MM1",
1409 .enable_mask = 0x1,
1410 .num_nodes = 12,
1411 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
1412 &qnm_camnoc_sf, &qnm_mdp,
1413 &qnm_mnoc_cfg, &qnm_rot,
1414 &qnm_vapss_hcp, &qnm_video,
1415 &qnm_video_cv_cpu, &qnm_video_cvp,
1416 &qnm_video_v_cpu, &qns_mem_noc_sf },
1417};

--- 26 unchanged lines hidden (view full) ---

1444 .name = "SH0",
1445 .keepalive = true,
1446 .num_nodes = 1,
1447 .nodes = { &qns_llcc },
1448};
1449
1450static struct qcom_icc_bcm bcm_sh1 = {
1451 .name = "SH1",
1408 .num_nodes = 12,
1409 .nodes = { &qnm_camnoc_hf, &qnm_camnoc_icp,
1410 &qnm_camnoc_sf, &qnm_mdp,
1411 &qnm_mnoc_cfg, &qnm_rot,
1412 &qnm_vapss_hcp, &qnm_video,
1413 &qnm_video_cv_cpu, &qnm_video_cvp,
1414 &qnm_video_v_cpu, &qns_mem_noc_sf },
1415};

--- 26 unchanged lines hidden (view full) ---

1442 .name = "SH0",
1443 .keepalive = true,
1444 .num_nodes = 1,
1445 .nodes = { &qns_llcc },
1446};
1447
1448static struct qcom_icc_bcm bcm_sh1 = {
1449 .name = "SH1",
1452 .enable_mask = 0x1,
1453 .num_nodes = 7,
1454 .nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1455 &qnm_nsp_gemnoc, &qnm_pcie,
1456 &qnm_snoc_gc, &qns_gem_noc_cnoc,
1457 &qns_pcie },
1458};
1459
1460static struct qcom_icc_bcm bcm_sn0 = {
1461 .name = "SN0",
1462 .keepalive = true,
1463 .num_nodes = 1,
1464 .nodes = { &qns_gemnoc_sf },
1465};
1466
1467static struct qcom_icc_bcm bcm_sn1 = {
1468 .name = "SN1",
1450 .num_nodes = 7,
1451 .nodes = { &alm_gpu_tcu, &alm_sys_tcu,
1452 &qnm_nsp_gemnoc, &qnm_pcie,
1453 &qnm_snoc_gc, &qns_gem_noc_cnoc,
1454 &qns_pcie },
1455};
1456
1457static struct qcom_icc_bcm bcm_sn0 = {
1458 .name = "SN0",
1459 .keepalive = true,
1460 .num_nodes = 1,
1461 .nodes = { &qns_gemnoc_sf },
1462};
1463
1464static struct qcom_icc_bcm bcm_sn1 = {
1465 .name = "SN1",
1469 .enable_mask = 0x1,
1470 .num_nodes = 4,
1471 .nodes = { &qhm_gic, &qxm_pimem,
1472 &xm_gic, &qns_gemnoc_gc },
1473};
1474
1475static struct qcom_icc_bcm bcm_sn2 = {
1476 .name = "SN2",
1477 .num_nodes = 1,

--- 15 unchanged lines hidden (view full) ---

1493static struct qcom_icc_bcm bcm_sn7 = {
1494 .name = "SN7",
1495 .num_nodes = 1,
1496 .nodes = { &qns_pcie_mem_noc },
1497};
1498
1499static struct qcom_icc_bcm bcm_acv_disp = {
1500 .name = "ACV",
1466 .num_nodes = 4,
1467 .nodes = { &qhm_gic, &qxm_pimem,
1468 &xm_gic, &qns_gemnoc_gc },
1469};
1470
1471static struct qcom_icc_bcm bcm_sn2 = {
1472 .name = "SN2",
1473 .num_nodes = 1,

--- 15 unchanged lines hidden (view full) ---

1489static struct qcom_icc_bcm bcm_sn7 = {
1490 .name = "SN7",
1491 .num_nodes = 1,
1492 .nodes = { &qns_pcie_mem_noc },
1493};
1494
1495static struct qcom_icc_bcm bcm_acv_disp = {
1496 .name = "ACV",
1501 .enable_mask = 0x1,
1502 .num_nodes = 1,
1503 .nodes = { &ebi_disp },
1504};
1505
1506static struct qcom_icc_bcm bcm_mc0_disp = {
1507 .name = "MC0",
1508 .num_nodes = 1,
1509 .nodes = { &ebi_disp },
1510};
1511
1512static struct qcom_icc_bcm bcm_mm0_disp = {
1513 .name = "MM0",
1514 .num_nodes = 1,
1515 .nodes = { &qns_mem_noc_hf_disp },
1516};
1517
1518static struct qcom_icc_bcm bcm_mm1_disp = {
1519 .name = "MM1",
1497 .num_nodes = 1,
1498 .nodes = { &ebi_disp },
1499};
1500
1501static struct qcom_icc_bcm bcm_mc0_disp = {
1502 .name = "MC0",
1503 .num_nodes = 1,
1504 .nodes = { &ebi_disp },
1505};
1506
1507static struct qcom_icc_bcm bcm_mm0_disp = {
1508 .name = "MM0",
1509 .num_nodes = 1,
1510 .nodes = { &qns_mem_noc_hf_disp },
1511};
1512
1513static struct qcom_icc_bcm bcm_mm1_disp = {
1514 .name = "MM1",
1520 .enable_mask = 0x1,
1521 .num_nodes = 3,
1522 .nodes = { &qnm_mdp_disp, &qnm_rot_disp,
1523 &qns_mem_noc_sf_disp },
1524};
1525
1526static struct qcom_icc_bcm bcm_sh0_disp = {
1527 .name = "SH0",
1528 .num_nodes = 1,
1529 .nodes = { &qns_llcc_disp },
1530};
1531
1532static struct qcom_icc_bcm bcm_sh1_disp = {
1533 .name = "SH1",
1515 .num_nodes = 3,
1516 .nodes = { &qnm_mdp_disp, &qnm_rot_disp,
1517 &qns_mem_noc_sf_disp },
1518};
1519
1520static struct qcom_icc_bcm bcm_sh0_disp = {
1521 .name = "SH0",
1522 .num_nodes = 1,
1523 .nodes = { &qns_llcc_disp },
1524};
1525
1526static struct qcom_icc_bcm bcm_sh1_disp = {
1527 .name = "SH1",
1534 .enable_mask = 0x1,
1535 .num_nodes = 1,
1536 .nodes = { &qnm_pcie_disp },
1537};
1538
1539static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1540};
1541
1542static struct qcom_icc_node * const aggre1_noc_nodes[] = {

--- 363 unchanged lines hidden --- 		1528 .num_nodes = 1,
1529 .nodes = { &qnm_pcie_disp },
1530};
1531
1532static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
1533};
1534
1535static struct qcom_icc_node * const aggre1_noc_nodes[] = {

--- 363 unchanged lines hidden ---