sm8250.c (cff66ace51e3acfcba3ab03f92adc9510830c365) sm8250.c (cde2f928ae7c59f72675bed13157b18fb7ddbcdd)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 *
5 */
6
7#include <linux/device.h>
8#include <linux/interconnect.h>
9#include <linux/interconnect-provider.h>
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
4 *
5 */
6
7#include <linux/device.h>
8#include <linux/interconnect.h>
9#include <linux/interconnect-provider.h>
10#include <linux/mod_devicetable.h>
11#include <linux/module.h>
10#include <linux/module.h>
12#include <linux/platform_device.h>
11#include <linux/of_platform.h>
13#include <dt-bindings/interconnect/qcom,sm8250.h>
14
15#include "bcm-voter.h"
16#include "icc-rpmh.h"
17#include "sm8250.h"
18
19DEFINE_QNODE(qhm_a1noc_cfg, SM8250_MASTER_A1NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A1NOC);
20DEFINE_QNODE(qhm_qspi, SM8250_MASTER_QSPI_0, 1, 4, SM8250_A1NOC_SNOC_SLV);

--- 139 unchanged lines hidden (view full) ---

160DEFINE_QNODE(qxs_pimem, SM8250_SLAVE_PIMEM, 1, 8);
161DEFINE_QNODE(srvc_snoc, SM8250_SLAVE_SERVICE_SNOC, 1, 4);
162DEFINE_QNODE(xs_pcie_0, SM8250_SLAVE_PCIE_0, 1, 8);
163DEFINE_QNODE(xs_pcie_1, SM8250_SLAVE_PCIE_1, 1, 8);
164DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8);
165DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4);
166DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8);
167
12#include <dt-bindings/interconnect/qcom,sm8250.h>
13
14#include "bcm-voter.h"
15#include "icc-rpmh.h"
16#include "sm8250.h"
17
18DEFINE_QNODE(qhm_a1noc_cfg, SM8250_MASTER_A1NOC_CFG, 1, 4, SM8250_SLAVE_SERVICE_A1NOC);
19DEFINE_QNODE(qhm_qspi, SM8250_MASTER_QSPI_0, 1, 4, SM8250_A1NOC_SNOC_SLV);

--- 139 unchanged lines hidden (view full) ---

159DEFINE_QNODE(qxs_pimem, SM8250_SLAVE_PIMEM, 1, 8);
160DEFINE_QNODE(srvc_snoc, SM8250_SLAVE_SERVICE_SNOC, 1, 4);
161DEFINE_QNODE(xs_pcie_0, SM8250_SLAVE_PCIE_0, 1, 8);
162DEFINE_QNODE(xs_pcie_1, SM8250_SLAVE_PCIE_1, 1, 8);
163DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8);
164DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4);
165DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8);
166
167static struct qcom_icc_node qup0_core_master = {
168 .name = "qup0_core_master",
169 .id = SM8250_MASTER_QUP_CORE_0,
170 .channels = 1,
171 .buswidth = 4,
172 .num_links = 1,
173 .links = { SM8250_SLAVE_QUP_CORE_0 },
174};
175
176static struct qcom_icc_node qup1_core_master = {
177 .name = "qup1_core_master",
178 .id = SM8250_MASTER_QUP_CORE_1,
179 .channels = 1,
180 .buswidth = 4,
181 .num_links = 1,
182 .links = { SM8250_SLAVE_QUP_CORE_1 },
183};
184
185static struct qcom_icc_node qup2_core_master = {
186 .name = "qup2_core_master",
187 .id = SM8250_MASTER_QUP_CORE_2,
188 .channels = 1,
189 .buswidth = 4,
190 .num_links = 1,
191 .links = { SM8250_SLAVE_QUP_CORE_2 },
192};
193
194static struct qcom_icc_node qup0_core_slave = {
195 .name = "qup0_core_slave",
196 .id = SM8250_SLAVE_QUP_CORE_0,
197 .channels = 1,
198 .buswidth = 4,
199};
200
201static struct qcom_icc_node qup1_core_slave = {
202 .name = "qup1_core_slave",
203 .id = SM8250_SLAVE_QUP_CORE_1,
204 .channels = 1,
205 .buswidth = 4,
206};
207
208static struct qcom_icc_node qup2_core_slave = {
209 .name = "qup2_core_slave",
210 .id = SM8250_SLAVE_QUP_CORE_2,
211 .channels = 1,
212 .buswidth = 4,
213};
214
168DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
169DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
170DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
171DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
172DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
173DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
174DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
175DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
215DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
216DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
217DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
218DEFINE_QBCM(bcm_mm0, "MM0", true, &qns_mem_noc_hf);
219DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
220DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
221DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
222DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
176DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2, &qhm_qup0);
223DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup2_core_master);
177DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
178DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp);
179DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
180DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
181DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
182DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_cfg, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie_modem_cfg, &qhs_pdm, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm0, &qhs_tlmm1, &qhs_tlmm2, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
183DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
184DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);

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189DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie_0, &xs_pcie_1);
190DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
191DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
192DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie);
193DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc);
194DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc);
195
196static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
224DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
225DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp);
226DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
227DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_gemnoc_sf);
228DEFINE_QBCM(bcm_co0, "CO0", false, &qns_cdsp_mem_noc);
229DEFINE_QBCM(bcm_cn0, "CN0", true, &qnm_snoc, &xm_qdss_dap, &qhs_a1_noc_cfg, &qhs_a2_noc_cfg, &qhs_ahb2phy0, &qhs_ahb2phy1, &qhs_aoss, &qhs_camera_cfg, &qhs_clk_ctl, &qhs_compute_dsp, &qhs_cpr_cx, &qhs_cpr_mmcx, &qhs_cpr_mx, &qhs_crypto0_cfg, &qhs_cx_rdpm, &qhs_dcc_cfg, &qhs_ddrss_cfg, &qhs_display_cfg, &qhs_gpuss_cfg, &qhs_imem_cfg, &qhs_ipa, &qhs_ipc_router, &qhs_lpass_cfg, &qhs_mnoc_cfg, &qhs_npu_cfg, &qhs_pcie0_cfg, &qhs_pcie1_cfg, &qhs_pcie_modem_cfg, &qhs_pdm, &qhs_pimem_cfg, &qhs_prng, &qhs_qdss_cfg, &qhs_qspi, &qhs_qup0, &qhs_qup1, &qhs_qup2, &qhs_sdc2, &qhs_sdc4, &qhs_snoc_cfg, &qhs_tcsr, &qhs_tlmm0, &qhs_tlmm1, &qhs_tlmm2, &qhs_tsif, &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg, &qhs_usb3_0, &qhs_usb3_1, &qhs_venus_cfg, &qhs_vsense_ctrl_cfg, &qns_cnoc_a2noc, &srvc_cnoc);
230DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
231DEFINE_QBCM(bcm_sn2, "SN2", false, &qns_gemnoc_gc);

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236DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie_0, &xs_pcie_1);
237DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre1_noc);
238DEFINE_QBCM(bcm_sn8, "SN8", false, &qnm_aggre2_noc);
239DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_gemnoc_pcie);
240DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc);
241DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc);
242
243static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
197 &bcm_qup0,
198 &bcm_sn12,
199};
200
201static struct qcom_icc_node * const aggre1_noc_nodes[] = {
202 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
203 [MASTER_QSPI_0] = &qhm_qspi,
204 [MASTER_QUP_1] = &qhm_qup1,
205 [MASTER_QUP_2] = &qhm_qup2,

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218 .nodes = aggre1_noc_nodes,
219 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
220 .bcms = aggre1_noc_bcms,
221 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
222};
223
224static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
225 &bcm_ce0,
244 &bcm_sn12,
245};
246
247static struct qcom_icc_node * const aggre1_noc_nodes[] = {
248 [MASTER_A1NOC_CFG] = &qhm_a1noc_cfg,
249 [MASTER_QSPI_0] = &qhm_qspi,
250 [MASTER_QUP_1] = &qhm_qup1,
251 [MASTER_QUP_2] = &qhm_qup2,

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264 .nodes = aggre1_noc_nodes,
265 .num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
266 .bcms = aggre1_noc_bcms,
267 .num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
268};
269
270static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
271 &bcm_ce0,
226 &bcm_qup0,
227 &bcm_sn12,
228};
229
272 &bcm_sn12,
273};
274
275static struct qcom_icc_bcm * const qup_virt_bcms[] = {
276 &bcm_qup0,
277};
278
279static struct qcom_icc_node *qup_virt_nodes[] = {
280 [MASTER_QUP_CORE_0] = &qup0_core_master,
281 [MASTER_QUP_CORE_1] = &qup1_core_master,
282 [MASTER_QUP_CORE_2] = &qup2_core_master,
283 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
284 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
285 [SLAVE_QUP_CORE_2] = &qup2_core_slave,
286};
287
288static const struct qcom_icc_desc sm8250_qup_virt = {
289 .nodes = qup_virt_nodes,
290 .num_nodes = ARRAY_SIZE(qup_virt_nodes),
291 .bcms = qup_virt_bcms,
292 .num_bcms = ARRAY_SIZE(qup_virt_bcms),
293};
294
230static struct qcom_icc_node * const aggre2_noc_nodes[] = {
231 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
232 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
233 [MASTER_QUP_0] = &qhm_qup0,
234 [MASTER_CNOC_A2NOC] = &qnm_cnoc,
235 [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
236 [MASTER_IPA] = &qxm_ipa,
237 [MASTER_PCIE] = &xm_pcie3_0,

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514 { .compatible = "qcom,sm8250-gem-noc",
515 .data = &sm8250_gem_noc},
516 { .compatible = "qcom,sm8250-mc-virt",
517 .data = &sm8250_mc_virt},
518 { .compatible = "qcom,sm8250-mmss-noc",
519 .data = &sm8250_mmss_noc},
520 { .compatible = "qcom,sm8250-npu-noc",
521 .data = &sm8250_npu_noc},
295static struct qcom_icc_node * const aggre2_noc_nodes[] = {
296 [MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
297 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
298 [MASTER_QUP_0] = &qhm_qup0,
299 [MASTER_CNOC_A2NOC] = &qnm_cnoc,
300 [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
301 [MASTER_IPA] = &qxm_ipa,
302 [MASTER_PCIE] = &xm_pcie3_0,

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579 { .compatible = "qcom,sm8250-gem-noc",
580 .data = &sm8250_gem_noc},
581 { .compatible = "qcom,sm8250-mc-virt",
582 .data = &sm8250_mc_virt},
583 { .compatible = "qcom,sm8250-mmss-noc",
584 .data = &sm8250_mmss_noc},
585 { .compatible = "qcom,sm8250-npu-noc",
586 .data = &sm8250_npu_noc},
587 { .compatible = "qcom,sm8250-qup-virt",
588 .data = &sm8250_qup_virt },
522 { .compatible = "qcom,sm8250-system-noc",
523 .data = &sm8250_system_noc},
524 { }
525};
526MODULE_DEVICE_TABLE(of, qnoc_of_match);
527
528static struct platform_driver qnoc_driver = {
529 .probe = qcom_icc_rpmh_probe,
530 .remove = qcom_icc_rpmh_remove,
531 .driver = {
532 .name = "qnoc-sm8250",
533 .of_match_table = qnoc_of_match,
534 },
535};
536module_platform_driver(qnoc_driver);
537
538MODULE_DESCRIPTION("Qualcomm SM8250 NoC driver");
539MODULE_LICENSE("GPL v2");
589 { .compatible = "qcom,sm8250-system-noc",
590 .data = &sm8250_system_noc},
591 { }
592};
593MODULE_DEVICE_TABLE(of, qnoc_of_match);
594
595static struct platform_driver qnoc_driver = {
596 .probe = qcom_icc_rpmh_probe,
597 .remove = qcom_icc_rpmh_remove,
598 .driver = {
599 .name = "qnoc-sm8250",
600 .of_match_table = qnoc_of_match,
601 },
602};
603module_platform_driver(qnoc_driver);
604
605MODULE_DESCRIPTION("Qualcomm SM8250 NoC driver");
606MODULE_LICENSE("GPL v2");