stm32-adc.c (446279168e030fd0ed68e2bba336bef8bb3da352) stm32-adc.c (d7705f35448ada5a04f15326404e40d4254c538d)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file is part of STM32 ADC driver
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7 */
8

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16#include <linux/iio/timer/stm32-timer-trigger.h>
17#include <linux/iio/trigger.h>
18#include <linux/iio/trigger_consumer.h>
19#include <linux/iio/triggered_buffer.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/iopoll.h>
23#include <linux/module.h>
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * This file is part of STM32 ADC driver
4 *
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
6 * Author: Fabrice Gasnier <fabrice.gasnier@st.com>.
7 */
8

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16#include <linux/iio/timer/stm32-timer-trigger.h>
17#include <linux/iio/trigger.h>
18#include <linux/iio/trigger_consumer.h>
19#include <linux/iio/triggered_buffer.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/iopoll.h>
23#include <linux/module.h>
24#include <linux/mod_devicetable.h>
24#include <linux/nvmem-consumer.h>
25#include <linux/platform_device.h>
26#include <linux/pm_runtime.h>
25#include <linux/nvmem-consumer.h>
26#include <linux/platform_device.h>
27#include <linux/pm_runtime.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
28#include <linux/property.h>
29
30#include "stm32-adc-core.h"
31
32/* Number of linear calibration shadow registers / LINCALRDYW control bits */
33#define STM32H7_LINCALFACT_NUM 6
34
35/* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
36#define STM32H7_BOOST_CLKRATE 20000000UL

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236 * @difsel: bitmask to set single-ended/differential channel
237 * @pcsel: bitmask to preselect channels on some devices
238 * @smpr_val: sampling time settings (e.g. smpr1 / smpr2)
239 * @cal: optional calibration data on some devices
240 * @vrefint: internal reference voltage data
241 * @chan_name: channel name array
242 * @num_diff: number of differential channels
243 * @int_ch: internal channel indexes array
29
30#include "stm32-adc-core.h"
31
32/* Number of linear calibration shadow registers / LINCALRDYW control bits */
33#define STM32H7_LINCALFACT_NUM 6
34
35/* BOOST bit must be set on STM32H7 when ADC clock is above 20MHz */
36#define STM32H7_BOOST_CLKRATE 20000000UL

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236 * @difsel: bitmask to set single-ended/differential channel
237 * @pcsel: bitmask to preselect channels on some devices
238 * @smpr_val: sampling time settings (e.g. smpr1 / smpr2)
239 * @cal: optional calibration data on some devices
240 * @vrefint: internal reference voltage data
241 * @chan_name: channel name array
242 * @num_diff: number of differential channels
243 * @int_ch: internal channel indexes array
244 * @nsmps: number of channels with optional sample time
244 */
245struct stm32_adc {
246 struct stm32_adc_common *common;
247 u32 offset;
248 const struct stm32_adc_cfg *cfg;
249 struct completion completion;
250 u16 buffer[STM32_ADC_MAX_SQ + 4] __aligned(8);
251 struct clk *clk;

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262 u32 difsel;
263 u32 pcsel;
264 u32 smpr_val[2];
265 struct stm32_adc_calib cal;
266 struct stm32_adc_vrefint vrefint;
267 char chan_name[STM32_ADC_CH_MAX][STM32_ADC_CH_SZ];
268 u32 num_diff;
269 int int_ch[STM32_ADC_INT_CH_NB];
245 */
246struct stm32_adc {
247 struct stm32_adc_common *common;
248 u32 offset;
249 const struct stm32_adc_cfg *cfg;
250 struct completion completion;
251 u16 buffer[STM32_ADC_MAX_SQ + 4] __aligned(8);
252 struct clk *clk;

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263 u32 difsel;
264 u32 pcsel;
265 u32 smpr_val[2];
266 struct stm32_adc_calib cal;
267 struct stm32_adc_vrefint vrefint;
268 char chan_name[STM32_ADC_CH_MAX][STM32_ADC_CH_SZ];
269 u32 num_diff;
270 int int_ch[STM32_ADC_INT_CH_NB];
271 int nsmps;
270};
271
272struct stm32_adc_diff_channel {
273 u32 vinp;
274 u32 vinn;
275};
276
277/**

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871}
872
873static void stm32h7_adc_disable(struct iio_dev *indio_dev)
874{
875 struct stm32_adc *adc = iio_priv(indio_dev);
876 int ret;
877 u32 val;
878
272};
273
274struct stm32_adc_diff_channel {
275 u32 vinp;
276 u32 vinn;
277};
278
279/**

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873}
874
875static void stm32h7_adc_disable(struct iio_dev *indio_dev)
876{
877 struct stm32_adc *adc = iio_priv(indio_dev);
878 int ret;
879 u32 val;
880
881 if (!(stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_ADEN))
882 return;
883
879 /* Disable ADC and wait until it's effectively disabled */
880 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
881 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
882 !(val & STM32H7_ADEN), 100,
883 STM32_ADC_TIMEOUT_US);
884 if (ret)
885 dev_warn(&indio_dev->dev, "Failed to disable\n");
886}

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1011{
1012 struct stm32_adc *adc = iio_priv(indio_dev);
1013 int ret;
1014 u32 val;
1015
1016 if (adc->cal.calibrated)
1017 return true;
1018
884 /* Disable ADC and wait until it's effectively disabled */
885 stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS);
886 ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val,
887 !(val & STM32H7_ADEN), 100,
888 STM32_ADC_TIMEOUT_US);
889 if (ret)
890 dev_warn(&indio_dev->dev, "Failed to disable\n");
891}

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1016{
1017 struct stm32_adc *adc = iio_priv(indio_dev);
1018 int ret;
1019 u32 val;
1020
1021 if (adc->cal.calibrated)
1022 return true;
1023
1024 /* ADC must be disabled for calibration */
1025 stm32h7_adc_disable(indio_dev);
1026
1019 /*
1020 * Select calibration mode:
1021 * - Offset calibration for single ended inputs
1022 * - No linearity calibration (do it later, before reading it)
1023 */
1024 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF);
1025 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN);
1026

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1509
1510 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask);
1511 pm_runtime_mark_last_busy(dev);
1512 pm_runtime_put_autosuspend(dev);
1513
1514 return ret;
1515}
1516
1027 /*
1028 * Select calibration mode:
1029 * - Offset calibration for single ended inputs
1030 * - No linearity calibration (do it later, before reading it)
1031 */
1032 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALDIF);
1033 stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_ADCALLIN);
1034

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1517
1518 ret = stm32_adc_conf_scan_seq(indio_dev, scan_mask);
1519 pm_runtime_mark_last_busy(dev);
1520 pm_runtime_put_autosuspend(dev);
1521
1522 return ret;
1523}
1524
1517static int stm32_adc_of_xlate(struct iio_dev *indio_dev,
1518 const struct of_phandle_args *iiospec)
1525static int stm32_adc_fwnode_xlate(struct iio_dev *indio_dev,
1526 const struct fwnode_reference_args *iiospec)
1519{
1520 int i;
1521
1522 for (i = 0; i < indio_dev->num_channels; i++)
1523 if (indio_dev->channels[i].channel == iiospec->args[0])
1524 return i;
1525
1526 return -EINVAL;

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1564}
1565
1566static const struct iio_info stm32_adc_iio_info = {
1567 .read_raw = stm32_adc_read_raw,
1568 .validate_trigger = stm32_adc_validate_trigger,
1569 .hwfifo_set_watermark = stm32_adc_set_watermark,
1570 .update_scan_mode = stm32_adc_update_scan_mode,
1571 .debugfs_reg_access = stm32_adc_debugfs_reg_access,
1527{
1528 int i;
1529
1530 for (i = 0; i < indio_dev->num_channels; i++)
1531 if (indio_dev->channels[i].channel == iiospec->args[0])
1532 return i;
1533
1534 return -EINVAL;

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1572}
1573
1574static const struct iio_info stm32_adc_iio_info = {
1575 .read_raw = stm32_adc_read_raw,
1576 .validate_trigger = stm32_adc_validate_trigger,
1577 .hwfifo_set_watermark = stm32_adc_set_watermark,
1578 .update_scan_mode = stm32_adc_update_scan_mode,
1579 .debugfs_reg_access = stm32_adc_debugfs_reg_access,
1572 .of_xlate = stm32_adc_of_xlate,
1580 .fwnode_xlate = stm32_adc_fwnode_xlate,
1573};
1574
1575static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc)
1576{
1577 struct dma_tx_state state;
1578 enum dma_status status;
1579
1580 status = dmaengine_tx_status(adc->dma_chan,

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1761 .name = "trigger_polarity_available",
1762 .shared = IIO_SHARED_BY_ALL,
1763 .read = iio_enum_available_read,
1764 .private = (uintptr_t)&stm32_adc_trig_pol,
1765 },
1766 {},
1767};
1768
1581};
1582
1583static unsigned int stm32_adc_dma_residue(struct stm32_adc *adc)
1584{
1585 struct dma_tx_state state;
1586 enum dma_status status;
1587
1588 status = dmaengine_tx_status(adc->dma_chan,

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1769 .name = "trigger_polarity_available",
1770 .shared = IIO_SHARED_BY_ALL,
1771 .read = iio_enum_available_read,
1772 .private = (uintptr_t)&stm32_adc_trig_pol,
1773 },
1774 {},
1775};
1776
1769static int stm32_adc_of_get_resolution(struct iio_dev *indio_dev)
1777static int stm32_adc_fw_get_resolution(struct iio_dev *indio_dev)
1770{
1778{
1771 struct device_node *node = indio_dev->dev.of_node;
1779 struct device *dev = &indio_dev->dev;
1772 struct stm32_adc *adc = iio_priv(indio_dev);
1773 unsigned int i;
1774 u32 res;
1775
1780 struct stm32_adc *adc = iio_priv(indio_dev);
1781 unsigned int i;
1782 u32 res;
1783
1776 if (of_property_read_u32(node, "assigned-resolution-bits", &res))
1784 if (device_property_read_u32(dev, "assigned-resolution-bits", &res))
1777 res = adc->cfg->adc_info->resolutions[0];
1778
1779 for (i = 0; i < adc->cfg->adc_info->num_res; i++)
1780 if (res == adc->cfg->adc_info->resolutions[i])
1781 break;
1782 if (i >= adc->cfg->adc_info->num_res) {
1783 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res);
1784 return -EINVAL;

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1852 adc->difsel |= BIT(chan->channel);
1853 /* Also add negative input to pre-selected channels */
1854 adc->pcsel |= BIT(chan->channel2);
1855 }
1856}
1857
1858static int stm32_adc_get_legacy_chan_count(struct iio_dev *indio_dev, struct stm32_adc *adc)
1859{
1785 res = adc->cfg->adc_info->resolutions[0];
1786
1787 for (i = 0; i < adc->cfg->adc_info->num_res; i++)
1788 if (res == adc->cfg->adc_info->resolutions[i])
1789 break;
1790 if (i >= adc->cfg->adc_info->num_res) {
1791 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res);
1792 return -EINVAL;

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1860 adc->difsel |= BIT(chan->channel);
1861 /* Also add negative input to pre-selected channels */
1862 adc->pcsel |= BIT(chan->channel2);
1863 }
1864}
1865
1866static int stm32_adc_get_legacy_chan_count(struct iio_dev *indio_dev, struct stm32_adc *adc)
1867{
1860 struct device_node *node = indio_dev->dev.of_node;
1868 struct device *dev = &indio_dev->dev;
1861 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
1862 int num_channels = 0, ret;
1863
1869 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
1870 int num_channels = 0, ret;
1871
1864 ret = of_property_count_u32_elems(node, "st,adc-channels");
1872 ret = device_property_count_u32(dev, "st,adc-channels");
1865 if (ret > adc_info->max_channels) {
1866 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
1867 return -EINVAL;
1868 } else if (ret > 0) {
1869 num_channels += ret;
1870 }
1871
1873 if (ret > adc_info->max_channels) {
1874 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n");
1875 return -EINVAL;
1876 } else if (ret > 0) {
1877 num_channels += ret;
1878 }
1879
1872 ret = of_property_count_elems_of_size(node, "st,adc-diff-channels",
1873 sizeof(struct stm32_adc_diff_channel));
1880 /*
1881 * each st,adc-diff-channels is a group of 2 u32 so we divide @ret
1882 * to get the *real* number of channels.
1883 */
1884 ret = device_property_count_u32(dev, "st,adc-diff-channels");
1885 if (ret < 0)
1886 return ret;
1887
1888 ret /= (int)(sizeof(struct stm32_adc_diff_channel) / sizeof(u32));
1874 if (ret > adc_info->max_channels) {
1875 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n");
1876 return -EINVAL;
1877 } else if (ret > 0) {
1878 adc->num_diff = ret;
1879 num_channels += ret;
1880 }
1881
1882 /* Optional sample time is provided either for each, or all channels */
1889 if (ret > adc_info->max_channels) {
1890 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n");
1891 return -EINVAL;
1892 } else if (ret > 0) {
1893 adc->num_diff = ret;
1894 num_channels += ret;
1895 }
1896
1897 /* Optional sample time is provided either for each, or all channels */
1883 ret = of_property_count_u32_elems(node, "st,min-sample-time-nsecs");
1884 if (ret > 1 && ret != num_channels) {
1898 adc->nsmps = device_property_count_u32(dev, "st,min-sample-time-nsecs");
1899 if (adc->nsmps > 1 && adc->nsmps != num_channels) {
1885 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n");
1886 return -EINVAL;
1887 }
1888
1889 return num_channels;
1890}
1891
1892static int stm32_adc_legacy_chan_init(struct iio_dev *indio_dev,
1893 struct stm32_adc *adc,
1900 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n");
1901 return -EINVAL;
1902 }
1903
1904 return num_channels;
1905}
1906
1907static int stm32_adc_legacy_chan_init(struct iio_dev *indio_dev,
1908 struct stm32_adc *adc,
1894 struct iio_chan_spec *channels)
1909 struct iio_chan_spec *channels,
1910 int nchans)
1895{
1911{
1896 struct device_node *node = indio_dev->dev.of_node;
1897 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
1898 struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX];
1912 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
1913 struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX];
1914 struct device *dev = &indio_dev->dev;
1899 u32 num_diff = adc->num_diff;
1900 int size = num_diff * sizeof(*diff) / sizeof(u32);
1915 u32 num_diff = adc->num_diff;
1916 int size = num_diff * sizeof(*diff) / sizeof(u32);
1901 int scan_index = 0, val, ret, i;
1902 struct property *prop;
1903 const __be32 *cur;
1904 u32 smp = 0;
1917 int scan_index = 0, ret, i, c;
1918 u32 smp = 0, smps[STM32_ADC_CH_MAX], chans[STM32_ADC_CH_MAX];
1905
1906 if (num_diff) {
1919
1920 if (num_diff) {
1907 ret = of_property_read_u32_array(node, "st,adc-diff-channels",
1908 (u32 *)diff, size);
1921 ret = device_property_read_u32_array(dev, "st,adc-diff-channels",
1922 (u32 *)diff, size);
1909 if (ret) {
1910 dev_err(&indio_dev->dev, "Failed to get diff channels %d\n", ret);
1911 return ret;
1912 }
1913
1914 for (i = 0; i < num_diff; i++) {
1915 if (diff[i].vinp >= adc_info->max_channels ||
1916 diff[i].vinn >= adc_info->max_channels) {

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1921
1922 stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
1923 diff[i].vinp, diff[i].vinn,
1924 scan_index, true);
1925 scan_index++;
1926 }
1927 }
1928
1923 if (ret) {
1924 dev_err(&indio_dev->dev, "Failed to get diff channels %d\n", ret);
1925 return ret;
1926 }
1927
1928 for (i = 0; i < num_diff; i++) {
1929 if (diff[i].vinp >= adc_info->max_channels ||
1930 diff[i].vinn >= adc_info->max_channels) {

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1935
1936 stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
1937 diff[i].vinp, diff[i].vinn,
1938 scan_index, true);
1939 scan_index++;
1940 }
1941 }
1942
1929 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) {
1930 if (val >= adc_info->max_channels) {
1931 dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
1943 ret = device_property_read_u32_array(dev, "st,adc-channels", chans,
1944 nchans);
1945 if (ret)
1946 return ret;
1947
1948 for (c = 0; c < nchans; c++) {
1949 if (chans[c] >= adc_info->max_channels) {
1950 dev_err(&indio_dev->dev, "Invalid channel %d\n",
1951 chans[c]);
1932 return -EINVAL;
1933 }
1934
1935 /* Channel can't be configured both as single-ended & diff */
1936 for (i = 0; i < num_diff; i++) {
1952 return -EINVAL;
1953 }
1954
1955 /* Channel can't be configured both as single-ended & diff */
1956 for (i = 0; i < num_diff; i++) {
1937 if (val == diff[i].vinp) {
1938 dev_err(&indio_dev->dev, "channel %d misconfigured\n", val);
1957 if (chans[c] == diff[i].vinp) {
1958 dev_err(&indio_dev->dev, "channel %d misconfigured\n", chans[c]);
1939 return -EINVAL;
1940 }
1941 }
1959 return -EINVAL;
1960 }
1961 }
1942 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val,
1943 0, scan_index, false);
1962 stm32_adc_chan_init_one(indio_dev, &channels[scan_index],
1963 chans[c], 0, scan_index, false);
1944 scan_index++;
1945 }
1946
1964 scan_index++;
1965 }
1966
1967 if (adc->nsmps > 0) {
1968 ret = device_property_read_u32_array(dev, "st,min-sample-time-nsecs",
1969 smps, adc->nsmps);
1970 if (ret)
1971 return ret;
1972 }
1973
1947 for (i = 0; i < scan_index; i++) {
1948 /*
1974 for (i = 0; i < scan_index; i++) {
1975 /*
1949 * Using of_property_read_u32_index(), smp value will only be
1950 * modified if valid u32 value can be decoded. This allows to
1951 * get either no value, 1 shared value for all indexes, or one
1952 * value per channel.
1976 * This check is used with the above logic so that smp value
1977 * will only be modified if valid u32 value can be decoded. This
1978 * allows to get either no value, 1 shared value for all indexes,
1979 * or one value per channel. The point is to have the same
1980 * behavior as 'of_property_read_u32_index()'.
1953 */
1981 */
1954 of_property_read_u32_index(node, "st,min-sample-time-nsecs", i, &smp);
1982 if (i < adc->nsmps)
1983 smp = smps[i];
1955
1956 /* Prepare sampling time settings */
1957 stm32_adc_smpr_init(adc, channels[i].channel, smp);
1958 }
1959
1960 return scan_index;
1961}
1962

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1994
1995 return 0;
1996}
1997
1998static int stm32_adc_generic_chan_init(struct iio_dev *indio_dev,
1999 struct stm32_adc *adc,
2000 struct iio_chan_spec *channels)
2001{
1984
1985 /* Prepare sampling time settings */
1986 stm32_adc_smpr_init(adc, channels[i].channel, smp);
1987 }
1988
1989 return scan_index;
1990}
1991

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2023
2024 return 0;
2025}
2026
2027static int stm32_adc_generic_chan_init(struct iio_dev *indio_dev,
2028 struct stm32_adc *adc,
2029 struct iio_chan_spec *channels)
2030{
2002 struct device_node *node = indio_dev->dev.of_node;
2003 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
2031 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
2004 struct device_node *child;
2032 struct fwnode_handle *child;
2005 const char *name;
2006 int val, scan_index = 0, ret;
2007 bool differential;
2008 u32 vin[2];
2009
2033 const char *name;
2034 int val, scan_index = 0, ret;
2035 bool differential;
2036 u32 vin[2];
2037
2010 for_each_available_child_of_node(node, child) {
2011 ret = of_property_read_u32(child, "reg", &val);
2038 device_for_each_child_node(&indio_dev->dev, child) {
2039 ret = fwnode_property_read_u32(child, "reg", &val);
2012 if (ret) {
2013 dev_err(&indio_dev->dev, "Missing channel index %d\n", ret);
2014 goto err;
2015 }
2016
2040 if (ret) {
2041 dev_err(&indio_dev->dev, "Missing channel index %d\n", ret);
2042 goto err;
2043 }
2044
2017 ret = of_property_read_string(child, "label", &name);
2045 ret = fwnode_property_read_string(child, "label", &name);
2018 /* label is optional */
2019 if (!ret) {
2020 if (strlen(name) >= STM32_ADC_CH_SZ) {
2021 dev_err(&indio_dev->dev, "Label %s exceeds %d characters\n",
2022 name, STM32_ADC_CH_SZ);
2023 ret = -EINVAL;
2024 goto err;
2025 }

--- 10 unchanged lines hidden (view full) ---

2036
2037 if (val >= adc_info->max_channels) {
2038 dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
2039 ret = -EINVAL;
2040 goto err;
2041 }
2042
2043 differential = false;
2046 /* label is optional */
2047 if (!ret) {
2048 if (strlen(name) >= STM32_ADC_CH_SZ) {
2049 dev_err(&indio_dev->dev, "Label %s exceeds %d characters\n",
2050 name, STM32_ADC_CH_SZ);
2051 ret = -EINVAL;
2052 goto err;
2053 }

--- 10 unchanged lines hidden (view full) ---

2064
2065 if (val >= adc_info->max_channels) {
2066 dev_err(&indio_dev->dev, "Invalid channel %d\n", val);
2067 ret = -EINVAL;
2068 goto err;
2069 }
2070
2071 differential = false;
2044 ret = of_property_read_u32_array(child, "diff-channels", vin, 2);
2072 ret = fwnode_property_read_u32_array(child, "diff-channels", vin, 2);
2045 /* diff-channels is optional */
2046 if (!ret) {
2047 differential = true;
2048 if (vin[0] != val || vin[1] >= adc_info->max_channels) {
2049 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n",
2050 vin[0], vin[1]);
2051 goto err;
2052 }
2053 } else if (ret != -EINVAL) {
2054 dev_err(&indio_dev->dev, "Invalid diff-channels property %d\n", ret);
2055 goto err;
2056 }
2057
2058 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val,
2059 vin[1], scan_index, differential);
2060
2073 /* diff-channels is optional */
2074 if (!ret) {
2075 differential = true;
2076 if (vin[0] != val || vin[1] >= adc_info->max_channels) {
2077 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n",
2078 vin[0], vin[1]);
2079 goto err;
2080 }
2081 } else if (ret != -EINVAL) {
2082 dev_err(&indio_dev->dev, "Invalid diff-channels property %d\n", ret);
2083 goto err;
2084 }
2085
2086 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val,
2087 vin[1], scan_index, differential);
2088
2061 ret = of_property_read_u32(child, "st,min-sample-time-ns", &val);
2089 ret = fwnode_property_read_u32(child, "st,min-sample-time-ns", &val);
2062 /* st,min-sample-time-ns is optional */
2063 if (!ret) {
2064 stm32_adc_smpr_init(adc, channels[scan_index].channel, val);
2065 if (differential)
2066 stm32_adc_smpr_init(adc, vin[1], val);
2067 } else if (ret != -EINVAL) {
2068 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-ns property %d\n",
2069 ret);
2070 goto err;
2071 }
2072
2073 scan_index++;
2074 }
2075
2076 return scan_index;
2077
2078err:
2090 /* st,min-sample-time-ns is optional */
2091 if (!ret) {
2092 stm32_adc_smpr_init(adc, channels[scan_index].channel, val);
2093 if (differential)
2094 stm32_adc_smpr_init(adc, vin[1], val);
2095 } else if (ret != -EINVAL) {
2096 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-ns property %d\n",
2097 ret);
2098 goto err;
2099 }
2100
2101 scan_index++;
2102 }
2103
2104 return scan_index;
2105
2106err:
2079 of_node_put(child);
2107 fwnode_handle_put(child);
2080
2081 return ret;
2082}
2083
2108
2109 return ret;
2110}
2111
2084static int stm32_adc_chan_of_init(struct iio_dev *indio_dev, bool timestamping)
2112static int stm32_adc_chan_fw_init(struct iio_dev *indio_dev, bool timestamping)
2085{
2113{
2086 struct device_node *node = indio_dev->dev.of_node;
2087 struct stm32_adc *adc = iio_priv(indio_dev);
2088 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
2089 struct iio_chan_spec *channels;
2090 int scan_index = 0, num_channels = 0, ret, i;
2091 bool legacy = false;
2092
2093 for (i = 0; i < STM32_ADC_INT_CH_NB; i++)
2094 adc->int_ch[i] = STM32_ADC_INT_CH_NONE;
2095
2114 struct stm32_adc *adc = iio_priv(indio_dev);
2115 const struct stm32_adc_info *adc_info = adc->cfg->adc_info;
2116 struct iio_chan_spec *channels;
2117 int scan_index = 0, num_channels = 0, ret, i;
2118 bool legacy = false;
2119
2120 for (i = 0; i < STM32_ADC_INT_CH_NB; i++)
2121 adc->int_ch[i] = STM32_ADC_INT_CH_NONE;
2122
2096 num_channels = of_get_available_child_count(node);
2123 num_channels = device_get_child_node_count(&indio_dev->dev);
2097 /* If no channels have been found, fallback to channels legacy properties. */
2098 if (!num_channels) {
2099 legacy = true;
2100
2101 ret = stm32_adc_get_legacy_chan_count(indio_dev, adc);
2102 if (!ret) {
2103 dev_err(indio_dev->dev.parent, "No channel found\n");
2104 return -ENODATA;

--- 14 unchanged lines hidden (view full) ---

2119 num_channels++;
2120
2121 channels = devm_kcalloc(&indio_dev->dev, num_channels,
2122 sizeof(struct iio_chan_spec), GFP_KERNEL);
2123 if (!channels)
2124 return -ENOMEM;
2125
2126 if (legacy)
2124 /* If no channels have been found, fallback to channels legacy properties. */
2125 if (!num_channels) {
2126 legacy = true;
2127
2128 ret = stm32_adc_get_legacy_chan_count(indio_dev, adc);
2129 if (!ret) {
2130 dev_err(indio_dev->dev.parent, "No channel found\n");
2131 return -ENODATA;

--- 14 unchanged lines hidden (view full) ---

2146 num_channels++;
2147
2148 channels = devm_kcalloc(&indio_dev->dev, num_channels,
2149 sizeof(struct iio_chan_spec), GFP_KERNEL);
2150 if (!channels)
2151 return -ENOMEM;
2152
2153 if (legacy)
2127 ret = stm32_adc_legacy_chan_init(indio_dev, adc, channels);
2154 ret = stm32_adc_legacy_chan_init(indio_dev, adc, channels,
2155 num_channels);
2128 else
2129 ret = stm32_adc_generic_chan_init(indio_dev, adc, channels);
2130 if (ret < 0)
2131 return ret;
2132 scan_index = ret;
2133
2134 if (timestamping) {
2135 struct iio_chan_spec *timestamp = &channels[scan_index];

--- 65 unchanged lines hidden (view full) ---

2201{
2202 struct iio_dev *indio_dev;
2203 struct device *dev = &pdev->dev;
2204 irqreturn_t (*handler)(int irq, void *p) = NULL;
2205 struct stm32_adc *adc;
2206 bool timestamping = false;
2207 int ret;
2208
2156 else
2157 ret = stm32_adc_generic_chan_init(indio_dev, adc, channels);
2158 if (ret < 0)
2159 return ret;
2160 scan_index = ret;
2161
2162 if (timestamping) {
2163 struct iio_chan_spec *timestamp = &channels[scan_index];

--- 65 unchanged lines hidden (view full) ---

2229{
2230 struct iio_dev *indio_dev;
2231 struct device *dev = &pdev->dev;
2232 irqreturn_t (*handler)(int irq, void *p) = NULL;
2233 struct stm32_adc *adc;
2234 bool timestamping = false;
2235 int ret;
2236
2209 if (!pdev->dev.of_node)
2210 return -ENODEV;
2211
2212 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
2213 if (!indio_dev)
2214 return -ENOMEM;
2215
2216 adc = iio_priv(indio_dev);
2217 adc->common = dev_get_drvdata(pdev->dev.parent);
2218 spin_lock_init(&adc->lock);
2219 init_completion(&adc->completion);
2237 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc));
2238 if (!indio_dev)
2239 return -ENOMEM;
2240
2241 adc = iio_priv(indio_dev);
2242 adc->common = dev_get_drvdata(pdev->dev.parent);
2243 spin_lock_init(&adc->lock);
2244 init_completion(&adc->completion);
2220 adc->cfg = (const struct stm32_adc_cfg *)
2221 of_match_device(dev->driver->of_match_table, dev)->data;
2245 adc->cfg = device_get_match_data(dev);
2222
2223 indio_dev->name = dev_name(&pdev->dev);
2246
2247 indio_dev->name = dev_name(&pdev->dev);
2224 indio_dev->dev.of_node = pdev->dev.of_node;
2248 device_set_node(&indio_dev->dev, dev_fwnode(&pdev->dev));
2225 indio_dev->info = &stm32_adc_iio_info;
2226 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED;
2227
2228 platform_set_drvdata(pdev, indio_dev);
2229
2249 indio_dev->info = &stm32_adc_iio_info;
2250 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED;
2251
2252 platform_set_drvdata(pdev, indio_dev);
2253
2230 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset);
2254 ret = device_property_read_u32(dev, "reg", &adc->offset);
2231 if (ret != 0) {
2232 dev_err(&pdev->dev, "missing reg property\n");
2233 return -EINVAL;
2234 }
2235
2236 adc->irq = platform_get_irq(pdev, 0);
2237 if (adc->irq < 0)
2238 return adc->irq;

--- 12 unchanged lines hidden (view full) ---

2251 if (ret == -ENOENT && !adc->cfg->clk_required) {
2252 adc->clk = NULL;
2253 } else {
2254 dev_err(&pdev->dev, "Can't get clock\n");
2255 return ret;
2256 }
2257 }
2258
2255 if (ret != 0) {
2256 dev_err(&pdev->dev, "missing reg property\n");
2257 return -EINVAL;
2258 }
2259
2260 adc->irq = platform_get_irq(pdev, 0);
2261 if (adc->irq < 0)
2262 return adc->irq;

--- 12 unchanged lines hidden (view full) ---

2275 if (ret == -ENOENT && !adc->cfg->clk_required) {
2276 adc->clk = NULL;
2277 } else {
2278 dev_err(&pdev->dev, "Can't get clock\n");
2279 return ret;
2280 }
2281 }
2282
2259 ret = stm32_adc_of_get_resolution(indio_dev);
2283 ret = stm32_adc_fw_get_resolution(indio_dev);
2260 if (ret < 0)
2261 return ret;
2262
2263 ret = stm32_adc_dma_request(dev, indio_dev);
2264 if (ret < 0)
2265 return ret;
2266
2267 if (!adc->dma_chan) {
2268 /* For PIO mode only, iio_pollfunc_store_time stores a timestamp
2269 * in the primary trigger IRQ handler and stm32_adc_trigger_handler
2270 * runs in the IRQ thread to push out buffer along with timestamp.
2271 */
2272 handler = &stm32_adc_trigger_handler;
2273 timestamping = true;
2274 }
2275
2284 if (ret < 0)
2285 return ret;
2286
2287 ret = stm32_adc_dma_request(dev, indio_dev);
2288 if (ret < 0)
2289 return ret;
2290
2291 if (!adc->dma_chan) {
2292 /* For PIO mode only, iio_pollfunc_store_time stores a timestamp
2293 * in the primary trigger IRQ handler and stm32_adc_trigger_handler
2294 * runs in the IRQ thread to push out buffer along with timestamp.
2295 */
2296 handler = &stm32_adc_trigger_handler;
2297 timestamping = true;
2298 }
2299
2276 ret = stm32_adc_chan_of_init(indio_dev, timestamping);
2300 ret = stm32_adc_chan_fw_init(indio_dev, timestamping);
2277 if (ret < 0)
2278 goto err_dma_disable;
2279
2280 ret = iio_triggered_buffer_setup(indio_dev,
2281 &iio_pollfunc_store_time, handler,
2282 &stm32_adc_buffer_setup_ops);
2283 if (ret) {
2284 dev_err(&pdev->dev, "buffer setup failed\n");

--- 173 unchanged lines hidden --- 		2301 if (ret < 0)
2302 goto err_dma_disable;
2303
2304 ret = iio_triggered_buffer_setup(indio_dev,
2305 &iio_pollfunc_store_time, handler,
2306 &stm32_adc_buffer_setup_ops);
2307 if (ret) {
2308 dev_err(&pdev->dev, "buffer setup failed\n");

--- 173 unchanged lines hidden ---