vic.c (3ff41673d5c6842e6668f95b0a14e5f6a74d043f) vic.c (f3779cb190a5a12d2e26fd5af724fb1384a9144f)
1/*
2 * Copyright (c) 2015, NVIDIA Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8

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21
22#include "drm.h"
23#include "falcon.h"
24#include "vic.h"
25
26struct vic_config {
27 const char *firmware;
28 unsigned int version;
1/*
2 * Copyright (c) 2015, NVIDIA Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8

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21
22#include "drm.h"
23#include "falcon.h"
24#include "vic.h"
25
26struct vic_config {
27 const char *firmware;
28 unsigned int version;
29 bool supports_sid;
29};
30
31struct vic {
32 struct falcon falcon;
33 bool booted;
34
35 void __iomem *regs;
36 struct tegra_drm_client client;

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100{
101 u32 fce_ucode_size, fce_bin_data_offset;
102 void *hdr;
103 int err = 0;
104
105 if (vic->booted)
106 return 0;
107
30};
31
32struct vic {
33 struct falcon falcon;
34 bool booted;
35
36 void __iomem *regs;
37 struct tegra_drm_client client;

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101{
102 u32 fce_ucode_size, fce_bin_data_offset;
103 void *hdr;
104 int err = 0;
105
106 if (vic->booted)
107 return 0;
108
109 if (vic->config->supports_sid) {
110 struct iommu_fwspec *spec = dev_iommu_fwspec_get(vic->dev);
111 u32 value;
112
113 value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) |
114 TRANSCFG_ATT(0, TRANSCFG_SID_HW);
115 vic_writel(vic, value, VIC_TFBIF_TRANSCFG);
116
117 if (spec && spec->num_ids > 0) {
118 value = spec->ids[0] & 0xffff;
119
120 vic_writel(vic, value, VIC_THI_STREAMID0);
121 vic_writel(vic, value, VIC_THI_STREAMID1);
122 }
123 }
124
108 /* setup clockgating registers */
109 vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) |
110 CG_IDLE_CG_EN |
111 CG_WAKEUP_DLY_CNT(4),
112 NV_PVIC_MISC_PRI_VIC_CG);
113
114 err = falcon_boot(&vic->falcon);
115 if (err < 0)

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309 .submit = tegra_drm_submit,
310};
311
312#define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
313
314static const struct vic_config vic_t124_config = {
315 .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE,
316 .version = 0x40,
125 /* setup clockgating registers */
126 vic_writel(vic, CG_IDLE_CG_DLY_CNT(4) |
127 CG_IDLE_CG_EN |
128 CG_WAKEUP_DLY_CNT(4),
129 NV_PVIC_MISC_PRI_VIC_CG);
130
131 err = falcon_boot(&vic->falcon);
132 if (err < 0)

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326 .submit = tegra_drm_submit,
327};
328
329#define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
330
331static const struct vic_config vic_t124_config = {
332 .firmware = NVIDIA_TEGRA_124_VIC_FIRMWARE,
333 .version = 0x40,
334 .supports_sid = false,
317};
318
319#define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin"
320
321static const struct vic_config vic_t210_config = {
322 .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE,
323 .version = 0x21,
335};
336
337#define NVIDIA_TEGRA_210_VIC_FIRMWARE "nvidia/tegra210/vic04_ucode.bin"
338
339static const struct vic_config vic_t210_config = {
340 .firmware = NVIDIA_TEGRA_210_VIC_FIRMWARE,
341 .version = 0x21,
342 .supports_sid = false,
324};
325
326#define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin"
327
328static const struct vic_config vic_t186_config = {
329 .firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE,
330 .version = 0x18,
343};
344
345#define NVIDIA_TEGRA_186_VIC_FIRMWARE "nvidia/tegra186/vic04_ucode.bin"
346
347static const struct vic_config vic_t186_config = {
348 .firmware = NVIDIA_TEGRA_186_VIC_FIRMWARE,
349 .version = 0x18,
350 .supports_sid = true,
331};
332
333#define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin"
334
335static const struct vic_config vic_t194_config = {
336 .firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE,
337 .version = 0x19,
351};
352
353#define NVIDIA_TEGRA_194_VIC_FIRMWARE "nvidia/tegra194/vic.bin"
354
355static const struct vic_config vic_t194_config = {
356 .firmware = NVIDIA_TEGRA_194_VIC_FIRMWARE,
357 .version = 0x19,
358 .supports_sid = true,
338};
339
340static const struct of_device_id vic_match[] = {
341 { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
342 { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
343 { .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config },
344 { .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config },
345 { },

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360
361static const struct of_device_id vic_match[] = {
362 { .compatible = "nvidia,tegra124-vic", .data = &vic_t124_config },
363 { .compatible = "nvidia,tegra210-vic", .data = &vic_t210_config },
364 { .compatible = "nvidia,tegra186-vic", .data = &vic_t186_config },
365 { .compatible = "nvidia,tegra194-vic", .data = &vic_t194_config },
366 { },

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