| hub.c (728d90bdc9e480dc93913e59a0aa3c896c7aa697) | hub.c (7e3c53a096a9e75b12e69f93ef1fbc7cb1b27297) |
|---|---|
| 1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6#include <linux/clk.h> 7#include <linux/delay.h> 8#include <linux/host1x.h> --- 443 unchanged lines hidden (view full) --- 452 453 value = INPUT_SCALER_VBYPASS | INPUT_SCALER_HBYPASS; 454 tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE); 455 456 /* disable compression */ 457 tegra_plane_writel(p, 0, DC_WINBUF_CDE_CONTROL); 458 459 bo = tegra_fb_get_plane(fb, 0); | 1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2017 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6#include <linux/clk.h> 7#include <linux/delay.h> 8#include <linux/host1x.h> --- 443 unchanged lines hidden (view full) --- 452 453 value = INPUT_SCALER_VBYPASS | INPUT_SCALER_HBYPASS; 454 tegra_plane_writel(p, value, DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE); 455 456 /* disable compression */ 457 tegra_plane_writel(p, 0, DC_WINBUF_CDE_CONTROL); 458 459 bo = tegra_fb_get_plane(fb, 0); |
| 460 base = bo->paddr; | 460 base = bo->iova; |
| 461 462 tegra_plane_writel(p, state->format, DC_WIN_COLOR_DEPTH); 463 tegra_plane_writel(p, 0, DC_WIN_PRECOMP_WGRP_PARAMS); 464 465 value = V_POSITION(plane->state->crtc_y) | 466 H_POSITION(plane->state->crtc_x); 467 tegra_plane_writel(p, value, DC_WIN_POSITION); 468 --- 500 unchanged lines hidden --- | 461 462 tegra_plane_writel(p, state->format, DC_WIN_COLOR_DEPTH); 463 tegra_plane_writel(p, 0, DC_WIN_PRECOMP_WGRP_PARAMS); 464 465 value = V_POSITION(plane->state->crtc_y) | 466 H_POSITION(plane->state->crtc_x); 467 tegra_plane_writel(p, value, DC_WIN_POSITION); 468 --- 500 unchanged lines hidden --- |