rv770.c (bf85279958da96cb4b11aac89b34f0424c3c120e) rv770.c (e32eb50dbe43862606a51caa94368ec6bd019434)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 343 unchanged lines hidden (view full) ---

352 WREG32(CP_ME_RAM_WADDR, 0);
353 WREG32(CP_ME_RAM_RADDR, 0);
354 return 0;
355}
356
357void r700_cp_fini(struct radeon_device *rdev)
358{
359 r700_cp_stop(rdev);
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 343 unchanged lines hidden (view full) ---

352 WREG32(CP_ME_RAM_WADDR, 0);
353 WREG32(CP_ME_RAM_RADDR, 0);
354 return 0;
355}
356
357void r700_cp_fini(struct radeon_device *rdev)
358{
359 r700_cp_stop(rdev);
360 radeon_ring_fini(rdev, &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]);
360 radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
361}
362
363/*
364 * Core functions
365 */
366static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
367 u32 num_tile_pipes,
368 u32 num_backends,

--- 669 unchanged lines hidden (view full) ---

1038 r700_vram_gtt_location(rdev, &rdev->mc);
1039 radeon_update_bandwidth_info(rdev);
1040
1041 return 0;
1042}
1043
1044static int rv770_startup(struct radeon_device *rdev)
1045{
361}
362
363/*
364 * Core functions
365 */
366static u32 r700_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
367 u32 num_tile_pipes,
368 u32 num_backends,

--- 669 unchanged lines hidden (view full) ---

1038 r700_vram_gtt_location(rdev, &rdev->mc);
1039 radeon_update_bandwidth_info(rdev);
1040
1041 return 0;
1042}
1043
1044static int rv770_startup(struct radeon_device *rdev)
1045{
1046 struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];
1046 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1047 int r;
1048
1049 /* enable pcie gen2 link */
1050 rv770_pcie_gen2_enable(rdev);
1051
1052 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1053 r = r600_init_microcode(rdev);
1054 if (r) {

--- 32 unchanged lines hidden (view full) ---

1087 r = r600_irq_init(rdev);
1088 if (r) {
1089 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1090 radeon_irq_kms_fini(rdev);
1091 return r;
1092 }
1093 r600_irq_set(rdev);
1094
1047 int r;
1048
1049 /* enable pcie gen2 link */
1050 rv770_pcie_gen2_enable(rdev);
1051
1052 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1053 r = r600_init_microcode(rdev);
1054 if (r) {

--- 32 unchanged lines hidden (view full) ---

1087 r = r600_irq_init(rdev);
1088 if (r) {
1089 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1090 radeon_irq_kms_fini(rdev);
1091 return r;
1092 }
1093 r600_irq_set(rdev);
1094
1095 r = radeon_ring_init(rdev, cp, cp->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1095 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1096 R600_CP_RB_RPTR, R600_CP_RB_WPTR);
1097 if (r)
1098 return r;
1099 r = rv770_cp_load_microcode(rdev);
1100 if (r)
1101 return r;
1102 r = r600_cp_resume(rdev);
1103 if (r)

--- 35 unchanged lines hidden (view full) ---

1139
1140}
1141
1142int rv770_suspend(struct radeon_device *rdev)
1143{
1144 r600_audio_fini(rdev);
1145 /* FIXME: we should wait for ring to be empty */
1146 r700_cp_stop(rdev);
1096 R600_CP_RB_RPTR, R600_CP_RB_WPTR);
1097 if (r)
1098 return r;
1099 r = rv770_cp_load_microcode(rdev);
1100 if (r)
1101 return r;
1102 r = r600_cp_resume(rdev);
1103 if (r)

--- 35 unchanged lines hidden (view full) ---

1139
1140}
1141
1142int rv770_suspend(struct radeon_device *rdev)
1143{
1144 r600_audio_fini(rdev);
1145 /* FIXME: we should wait for ring to be empty */
1146 r700_cp_stop(rdev);
1147 rdev->cp[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1147 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1148 r600_irq_suspend(rdev);
1149 radeon_wb_disable(rdev);
1150 rv770_pcie_gart_disable(rdev);
1151 r600_blit_suspend(rdev);
1152
1153 return 0;
1154}
1155

--- 56 unchanged lines hidden (view full) ---

1212 r = radeon_bo_init(rdev);
1213 if (r)
1214 return r;
1215
1216 r = radeon_irq_kms_init(rdev);
1217 if (r)
1218 return r;
1219
1148 r600_irq_suspend(rdev);
1149 radeon_wb_disable(rdev);
1150 rv770_pcie_gart_disable(rdev);
1151 r600_blit_suspend(rdev);
1152
1153 return 0;
1154}
1155

--- 56 unchanged lines hidden (view full) ---

1212 r = radeon_bo_init(rdev);
1213 if (r)
1214 return r;
1215
1216 r = radeon_irq_kms_init(rdev);
1217 if (r)
1218 return r;
1219
1220 rdev->cp[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
1221 r600_ring_init(rdev, &rdev->cp[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
1220 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
1221 r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
1222
1223 rdev->ih.ring_obj = NULL;
1224 r600_ih_ring_init(rdev, 64 * 1024);
1225
1226 r = r600_pcie_gart_init(rdev);
1227 if (r)
1228 return r;
1229

--- 128 unchanged lines hidden --- 		1222
1223 rdev->ih.ring_obj = NULL;
1224 r600_ih_ring_init(rdev, 64 * 1024);
1225
1226 r = r600_pcie_gart_init(rdev);
1227 if (r)
1228 return r;
1229

--- 128 unchanged lines hidden ---