rv770.c (0482e3c6f704d25b6a4e3c940caeeacece4e6d74) rv770.c (961fb597c17e2e4f55407d56b7211c188ab41eff)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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511 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
512
513 /* setup tiling, simd, pipe config */
514 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
515
516 switch (rdev->config.rv770.max_tile_pipes) {
517 case 1:
518 gb_tiling_config |= PIPE_TILING(0);
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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511 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
512
513 /* setup tiling, simd, pipe config */
514 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
515
516 switch (rdev->config.rv770.max_tile_pipes) {
517 case 1:
518 gb_tiling_config |= PIPE_TILING(0);
519 rdev->config.rv770.tiling_npipes = 1;
519 break;
520 case 2:
521 gb_tiling_config |= PIPE_TILING(1);
520 break;
521 case 2:
522 gb_tiling_config |= PIPE_TILING(1);
523 rdev->config.rv770.tiling_npipes = 2;
522 break;
523 case 4:
524 gb_tiling_config |= PIPE_TILING(2);
524 break;
525 case 4:
526 gb_tiling_config |= PIPE_TILING(2);
527 rdev->config.rv770.tiling_npipes = 4;
525 break;
526 case 8:
527 gb_tiling_config |= PIPE_TILING(3);
528 break;
529 case 8:
530 gb_tiling_config |= PIPE_TILING(3);
531 rdev->config.rv770.tiling_npipes = 8;
528 break;
529 default:
530 break;
531 }
532
533 if (rdev->family == CHIP_RV770)
534 gb_tiling_config |= BANK_TILING(1);
535 else
536 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
532 break;
533 default:
534 break;
535 }
536
537 if (rdev->family == CHIP_RV770)
538 gb_tiling_config |= BANK_TILING(1);
539 else
540 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
541 rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
537
538 gb_tiling_config |= GROUP_SIZE(0);
542
543 gb_tiling_config |= GROUP_SIZE(0);
544 rdev->config.rv770.tiling_group_size = 256;
539
540 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
541 gb_tiling_config |= ROW_TILING(3);
542 gb_tiling_config |= SAMPLE_SPLIT(3);
543 } else {
544 gb_tiling_config |=
545 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
546 gb_tiling_config |=

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824 /* gtt_size is setup by radeon_agp_init */
825 rdev->mc.gtt_location = rdev->mc.agp_base;
826 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
827 /* Try to put vram before or after AGP because we
828 * we want SYSTEM_APERTURE to cover both VRAM and
829 * AGP so that GPU can catch out of VRAM/AGP access
830 */
831 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
545
546 if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
547 gb_tiling_config |= ROW_TILING(3);
548 gb_tiling_config |= SAMPLE_SPLIT(3);
549 } else {
550 gb_tiling_config |=
551 ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
552 gb_tiling_config |=

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830 /* gtt_size is setup by radeon_agp_init */
831 rdev->mc.gtt_location = rdev->mc.agp_base;
832 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
833 /* Try to put vram before or after AGP because we
834 * we want SYSTEM_APERTURE to cover both VRAM and
835 * AGP so that GPU can catch out of VRAM/AGP access
836 */
837 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
832 /* Enough place before */
838 /* Enought place before */
833 rdev->mc.vram_location = rdev->mc.gtt_location -
834 rdev->mc.mc_vram_size;
835 } else if (tmp > rdev->mc.mc_vram_size) {
839 rdev->mc.vram_location = rdev->mc.gtt_location -
840 rdev->mc.mc_vram_size;
841 } else if (tmp > rdev->mc.mc_vram_size) {
836 /* Enough place after */
842 /* Enought place after */
837 rdev->mc.vram_location = rdev->mc.gtt_location +
838 rdev->mc.gtt_size;
839 } else {
840 /* Try to setup VRAM then AGP might not
841 * not work on some card
842 */
843 rdev->mc.vram_location = 0x00000000UL;
844 rdev->mc.gtt_location = rdev->mc.mc_vram_size;

--- 265 unchanged lines hidden --- 		843 rdev->mc.vram_location = rdev->mc.gtt_location +
844 rdev->mc.gtt_size;
845 } else {
846 /* Try to setup VRAM then AGP might not
847 * not work on some card
848 */
849 rdev->mc.vram_location = 0x00000000UL;
850 rdev->mc.gtt_location = rdev->mc.mc_vram_size;

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