rs400.c (0b28330e39bbe0ffee4c56b09fc415fcec595ea3) rs400.c (ce8f53709bf440100cb9d31b1303291551cf517f)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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238 }
239 DRM_UDELAY(1);
240 }
241 return -1;
242}
243
244void rs400_gpu_init(struct radeon_device *rdev)
245{
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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238 }
239 DRM_UDELAY(1);
240 }
241 return -1;
242}
243
244void rs400_gpu_init(struct radeon_device *rdev)
245{
246 /* FIXME: HDP same place on rs400 ? */
247 r100_hdp_reset(rdev);
248 /* FIXME: is this correct ? */
249 r420_pipes_init(rdev);
250 if (rs400_mc_wait_for_idle(rdev)) {
251 printk(KERN_WARNING "rs400: Failed to wait MC idle while "
252 "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
253 }
254}
255

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428{
429 /* Make sur GART are not working */
430 rs400_gart_disable(rdev);
431 /* Resume clock before doing reset */
432 r300_clock_startup(rdev);
433 /* setup MC before calling post tables */
434 rs400_mc_program(rdev);
435 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
246 /* FIXME: is this correct ? */
247 r420_pipes_init(rdev);
248 if (rs400_mc_wait_for_idle(rdev)) {
249 printk(KERN_WARNING "rs400: Failed to wait MC idle while "
250 "programming pipes. Bad things might happen. %08x\n", RREG32(0x150));
251 }
252}
253

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426{
427 /* Make sur GART are not working */
428 rs400_gart_disable(rdev);
429 /* Resume clock before doing reset */
430 r300_clock_startup(rdev);
431 /* setup MC before calling post tables */
432 rs400_mc_program(rdev);
433 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
436 if (radeon_gpu_reset(rdev)) {
434 if (radeon_asic_reset(rdev)) {
437 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
438 RREG32(R_000E40_RBBM_STATUS),
439 RREG32(R_0007C0_CP_STAT));
440 }
441 /* post */
442 radeon_combios_asic_init(rdev->ddev);
443 /* Resume clock after posting */
444 r300_clock_startup(rdev);

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453 r100_wb_disable(rdev);
454 r100_irq_disable(rdev);
455 rs400_gart_disable(rdev);
456 return 0;
457}
458
459void rs400_fini(struct radeon_device *rdev)
460{
435 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
436 RREG32(R_000E40_RBBM_STATUS),
437 RREG32(R_0007C0_CP_STAT));
438 }
439 /* post */
440 radeon_combios_asic_init(rdev->ddev);
441 /* Resume clock after posting */
442 r300_clock_startup(rdev);

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451 r100_wb_disable(rdev);
452 r100_irq_disable(rdev);
453 rs400_gart_disable(rdev);
454 return 0;
455}
456
457void rs400_fini(struct radeon_device *rdev)
458{
461 radeon_pm_fini(rdev);
462 r100_cp_fini(rdev);
463 r100_wb_fini(rdev);
464 r100_ib_fini(rdev);
465 radeon_gem_fini(rdev);
466 rs400_gart_fini(rdev);
467 radeon_irq_kms_fini(rdev);
468 radeon_fence_driver_fini(rdev);
469 radeon_bo_fini(rdev);

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492 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
493 return -EINVAL;
494 } else {
495 r = radeon_combios_init(rdev);
496 if (r)
497 return r;
498 }
499 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
459 r100_cp_fini(rdev);
460 r100_wb_fini(rdev);
461 r100_ib_fini(rdev);
462 radeon_gem_fini(rdev);
463 rs400_gart_fini(rdev);
464 radeon_irq_kms_fini(rdev);
465 radeon_fence_driver_fini(rdev);
466 radeon_bo_fini(rdev);

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489 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
490 return -EINVAL;
491 } else {
492 r = radeon_combios_init(rdev);
493 if (r)
494 return r;
495 }
496 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
500 if (radeon_gpu_reset(rdev)) {
497 if (radeon_asic_reset(rdev)) {
501 dev_warn(rdev->dev,
502 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
503 RREG32(R_000E40_RBBM_STATUS),
504 RREG32(R_0007C0_CP_STAT));
505 }
506 /* check if cards are posted or not */
507 if (radeon_boot_test_post_card(rdev) == false)
508 return -EINVAL;
509
510 /* Initialize clocks */
511 radeon_get_clock_info(rdev->ddev);
498 dev_warn(rdev->dev,
499 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
500 RREG32(R_000E40_RBBM_STATUS),
501 RREG32(R_0007C0_CP_STAT));
502 }
503 /* check if cards are posted or not */
504 if (radeon_boot_test_post_card(rdev) == false)
505 return -EINVAL;
506
507 /* Initialize clocks */
508 radeon_get_clock_info(rdev->ddev);
512 /* Initialize power management */
513 radeon_pm_init(rdev);
514 /* initialize memory controller */
515 rs400_mc_init(rdev);
516 /* Fence driver */
517 r = radeon_fence_driver_init(rdev);
518 if (r)
519 return r;
520 r = radeon_irq_kms_init(rdev);
521 if (r)

--- 23 unchanged lines hidden --- 		509 /* initialize memory controller */
510 rs400_mc_init(rdev);
511 /* Fence driver */
512 r = radeon_fence_driver_init(rdev);
513 if (r)
514 return r;
515 r = radeon_irq_kms_init(rdev);
516 if (r)

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