radeon.h (0482e3c6f704d25b6a4e3c940caeeacece4e6d74) radeon.h (961fb597c17e2e4f55407d56b7211c188ab41eff)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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84extern int radeon_agpmode;
85extern int radeon_vram_limit;
86extern int radeon_gart_size;
87extern int radeon_benchmarking;
88extern int radeon_testing;
89extern int radeon_connector_table;
90extern int radeon_tv;
91extern int radeon_new_pll;
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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84extern int radeon_agpmode;
85extern int radeon_vram_limit;
86extern int radeon_gart_size;
87extern int radeon_benchmarking;
88extern int radeon_testing;
89extern int radeon_connector_table;
90extern int radeon_tv;
91extern int radeon_new_pll;
92extern int radeon_dynpm;
92extern int radeon_audio;
93
94/*
95 * Copy from radeon_drv.h so we don't have to include both and have conflicting
96 * symbol;
97 */
98#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
99#define RADEON_IB_POOL_SIZE 16

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132
133
134/*
135 * Clocks
136 */
137struct radeon_clock {
138 struct radeon_pll p1pll;
139 struct radeon_pll p2pll;
93extern int radeon_audio;
94
95/*
96 * Copy from radeon_drv.h so we don't have to include both and have conflicting
97 * symbol;
98 */
99#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
100#define RADEON_IB_POOL_SIZE 16

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133
134
135/*
136 * Clocks
137 */
138struct radeon_clock {
139 struct radeon_pll p1pll;
140 struct radeon_pll p2pll;
141 struct radeon_pll dcpll;
140 struct radeon_pll spll;
141 struct radeon_pll mpll;
142 /* 10 Khz units */
143 uint32_t default_mclk;
144 uint32_t default_sclk;
142 struct radeon_pll spll;
143 struct radeon_pll mpll;
144 /* 10 Khz units */
145 uint32_t default_mclk;
146 uint32_t default_sclk;
147 uint32_t default_dispclk;
148 uint32_t dp_extclk;
145};
146
147/*
148 * Power management
149 */
150int radeon_pm_init(struct radeon_device *rdev);
149};
150
151/*
152 * Power management
153 */
154int radeon_pm_init(struct radeon_device *rdev);
155void radeon_pm_compute_clocks(struct radeon_device *rdev);
156void radeon_combios_get_power_modes(struct radeon_device *rdev);
157void radeon_atombios_get_power_modes(struct radeon_device *rdev);
151
152/*
153 * Fences.
154 */
155struct radeon_fence_driver {
156 uint32_t scratch_reg;
157 atomic_t seq;
158 uint32_t last_seq;

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342/*
343 * IRQS.
344 */
345struct radeon_irq {
346 bool installed;
347 bool sw_int;
348 /* FIXME: use a define max crtc rather than hardcode it */
349 bool crtc_vblank_int[2];
158
159/*
160 * Fences.
161 */
162struct radeon_fence_driver {
163 uint32_t scratch_reg;
164 atomic_t seq;
165 uint32_t last_seq;

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349/*
350 * IRQS.
351 */
352struct radeon_irq {
353 bool installed;
354 bool sw_int;
355 /* FIXME: use a define max crtc rather than hardcode it */
356 bool crtc_vblank_int[2];
357 wait_queue_head_t vblank_queue;
350 /* FIXME: use defines for max hpd/dacs */
351 bool hpd[6];
352 spinlock_t sw_lock;
353 int sw_refcount;
354};
355
356int radeon_irq_kms_init(struct radeon_device *rdev);
357void radeon_irq_kms_fini(struct radeon_device *rdev);

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373/*
374 * locking -
375 * mutex protects scheduled_ibs, ready, alloc_bm
376 */
377struct radeon_ib_pool {
378 struct mutex mutex;
379 struct radeon_bo *robj;
380 struct list_head scheduled_ibs;
358 /* FIXME: use defines for max hpd/dacs */
359 bool hpd[6];
360 spinlock_t sw_lock;
361 int sw_refcount;
362};
363
364int radeon_irq_kms_init(struct radeon_device *rdev);
365void radeon_irq_kms_fini(struct radeon_device *rdev);

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381/*
382 * locking -
383 * mutex protects scheduled_ibs, ready, alloc_bm
384 */
385struct radeon_ib_pool {
386 struct mutex mutex;
387 struct radeon_bo *robj;
388 struct list_head scheduled_ibs;
389 struct list_head bogus_ib;
381 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
382 bool ready;
383 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
384};
385
386struct radeon_cp {
387 struct radeon_bo *ring_obj;
388 volatile uint32_t *ring;

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427};
428
429int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
430void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
431int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
432int radeon_ib_pool_init(struct radeon_device *rdev);
433void radeon_ib_pool_fini(struct radeon_device *rdev);
434int radeon_ib_test(struct radeon_device *rdev);
390 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
391 bool ready;
392 DECLARE_BITMAP(alloc_bm, RADEON_IB_POOL_SIZE);
393};
394
395struct radeon_cp {
396 struct radeon_bo *ring_obj;
397 volatile uint32_t *ring;

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436};
437
438int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
439void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
440int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
441int radeon_ib_pool_init(struct radeon_device *rdev);
442void radeon_ib_pool_fini(struct radeon_device *rdev);
443int radeon_ib_test(struct radeon_device *rdev);
444extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
435/* Ring access between begin & end cannot sleep */
436void radeon_ring_free_size(struct radeon_device *rdev);
437int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
438void radeon_ring_unlock_commit(struct radeon_device *rdev);
439void radeon_ring_unlock_undo(struct radeon_device *rdev);
440int radeon_ring_test(struct radeon_device *rdev);
441int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
442void radeon_ring_fini(struct radeon_device *rdev);

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564 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
565 * @needed_bandwidth: current bandwidth needs
566 *
567 * It keeps track of various data needed to take powermanagement decision.
568 * Bandwith need is used to determine minimun clock of the GPU and memory.
569 * Equation between gpu/memory clock and available bandwidth is hw dependent
570 * (type of memory, bus size, efficiency, ...)
571 */
445/* Ring access between begin & end cannot sleep */
446void radeon_ring_free_size(struct radeon_device *rdev);
447int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
448void radeon_ring_unlock_commit(struct radeon_device *rdev);
449void radeon_ring_unlock_undo(struct radeon_device *rdev);
450int radeon_ring_test(struct radeon_device *rdev);
451int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
452void radeon_ring_fini(struct radeon_device *rdev);

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574 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
575 * @needed_bandwidth: current bandwidth needs
576 *
577 * It keeps track of various data needed to take powermanagement decision.
578 * Bandwith need is used to determine minimun clock of the GPU and memory.
579 * Equation between gpu/memory clock and available bandwidth is hw dependent
580 * (type of memory, bus size, efficiency, ...)
581 */
582enum radeon_pm_state {
583 PM_STATE_DISABLED,
584 PM_STATE_MINIMUM,
585 PM_STATE_PAUSED,
586 PM_STATE_ACTIVE
587};
588enum radeon_pm_action {
589 PM_ACTION_NONE,
590 PM_ACTION_MINIMUM,
591 PM_ACTION_DOWNCLOCK,
592 PM_ACTION_UPCLOCK
593};
594
595enum radeon_voltage_type {
596 VOLTAGE_NONE = 0,
597 VOLTAGE_GPIO,
598 VOLTAGE_VDDC,
599 VOLTAGE_SW
600};
601
602enum radeon_pm_state_type {
603 POWER_STATE_TYPE_DEFAULT,
604 POWER_STATE_TYPE_POWERSAVE,
605 POWER_STATE_TYPE_BATTERY,
606 POWER_STATE_TYPE_BALANCED,
607 POWER_STATE_TYPE_PERFORMANCE,
608};
609
610enum radeon_pm_clock_mode_type {
611 POWER_MODE_TYPE_DEFAULT,
612 POWER_MODE_TYPE_LOW,
613 POWER_MODE_TYPE_MID,
614 POWER_MODE_TYPE_HIGH,
615};
616
617struct radeon_voltage {
618 enum radeon_voltage_type type;
619 /* gpio voltage */
620 struct radeon_gpio_rec gpio;
621 u32 delay; /* delay in usec from voltage drop to sclk change */
622 bool active_high; /* voltage drop is active when bit is high */
623 /* VDDC voltage */
624 u8 vddc_id; /* index into vddc voltage table */
625 u8 vddci_id; /* index into vddci voltage table */
626 bool vddci_enabled;
627 /* r6xx+ sw */
628 u32 voltage;
629};
630
631struct radeon_pm_non_clock_info {
632 /* pcie lanes */
633 int pcie_lanes;
634 /* standardized non-clock flags */
635 u32 flags;
636};
637
638struct radeon_pm_clock_info {
639 /* memory clock */
640 u32 mclk;
641 /* engine clock */
642 u32 sclk;
643 /* voltage info */
644 struct radeon_voltage voltage;
645 /* standardized clock flags - not sure we'll need these */
646 u32 flags;
647};
648
649struct radeon_power_state {
650 enum radeon_pm_state_type type;
651 /* XXX: use a define for num clock modes */
652 struct radeon_pm_clock_info clock_info[8];
653 /* number of valid clock modes in this power state */
654 int num_clock_modes;
655 /* currently selected clock mode */
656 struct radeon_pm_clock_info *current_clock_mode;
657 struct radeon_pm_clock_info *requested_clock_mode;
658 struct radeon_pm_clock_info *default_clock_mode;
659 /* non clock info about this state */
660 struct radeon_pm_non_clock_info non_clock_info;
661 bool voltage_drop_active;
662};
663
572struct radeon_pm {
664struct radeon_pm {
665 struct mutex mutex;
666 struct delayed_work idle_work;
667 enum radeon_pm_state state;
668 enum radeon_pm_action planned_action;
669 unsigned long action_timeout;
670 bool downclocked;
671 int active_crtcs;
672 int req_vblank;
573 fixed20_12 max_bandwidth;
574 fixed20_12 igp_sideport_mclk;
575 fixed20_12 igp_system_mclk;
576 fixed20_12 igp_ht_link_clk;
577 fixed20_12 igp_ht_link_width;
578 fixed20_12 k8_bandwidth;
579 fixed20_12 sideport_bandwidth;
580 fixed20_12 ht_bandwidth;
581 fixed20_12 core_bandwidth;
582 fixed20_12 sclk;
583 fixed20_12 needed_bandwidth;
673 fixed20_12 max_bandwidth;
674 fixed20_12 igp_sideport_mclk;
675 fixed20_12 igp_system_mclk;
676 fixed20_12 igp_ht_link_clk;
677 fixed20_12 igp_ht_link_width;
678 fixed20_12 k8_bandwidth;
679 fixed20_12 sideport_bandwidth;
680 fixed20_12 ht_bandwidth;
681 fixed20_12 core_bandwidth;
682 fixed20_12 sclk;
683 fixed20_12 needed_bandwidth;
684 /* XXX: use a define for num power modes */
685 struct radeon_power_state power_state[8];
686 /* number of valid power states */
687 int num_power_states;
688 struct radeon_power_state *current_power_state;
689 struct radeon_power_state *requested_power_state;
690 struct radeon_power_state *default_power_state;
584};
585
586
587/*
588 * Benchmarking
589 */
590void radeon_benchmark(struct radeon_device *rdev);
591

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645 uint64_t src_offset,
646 uint64_t dst_offset,
647 unsigned num_pages,
648 struct radeon_fence *fence);
649 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
650 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
651 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
652 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
691};
692
693
694/*
695 * Benchmarking
696 */
697void radeon_benchmark(struct radeon_device *rdev);
698

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752 uint64_t src_offset,
753 uint64_t dst_offset,
754 unsigned num_pages,
755 struct radeon_fence *fence);
756 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
757 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
758 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
759 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
760 int (*get_pcie_lanes)(struct radeon_device *rdev);
653 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
654 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
655 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
656 uint32_t tiling_flags, uint32_t pitch,
657 uint32_t offset, uint32_t obj_size);
658 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
659 void (*bandwidth_update)(struct radeon_device *rdev);
660 void (*hpd_init)(struct radeon_device *rdev);

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695 unsigned max_threads;
696 unsigned max_stack_entries;
697 unsigned max_hw_contexts;
698 unsigned max_gs_threads;
699 unsigned sx_max_export_size;
700 unsigned sx_max_export_pos_size;
701 unsigned sx_max_export_smx_size;
702 unsigned sq_num_cf_insts;
761 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
762 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
763 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
764 uint32_t tiling_flags, uint32_t pitch,
765 uint32_t offset, uint32_t obj_size);
766 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
767 void (*bandwidth_update)(struct radeon_device *rdev);
768 void (*hpd_init)(struct radeon_device *rdev);

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803 unsigned max_threads;
804 unsigned max_stack_entries;
805 unsigned max_hw_contexts;
806 unsigned max_gs_threads;
807 unsigned sx_max_export_size;
808 unsigned sx_max_export_pos_size;
809 unsigned sx_max_export_smx_size;
810 unsigned sq_num_cf_insts;
811 unsigned tiling_nbanks;
812 unsigned tiling_npipes;
813 unsigned tiling_group_size;
703};
704
705struct rv770_asic {
706 unsigned max_pipes;
707 unsigned max_tile_pipes;
708 unsigned max_simds;
709 unsigned max_backends;
710 unsigned max_gprs;

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715 unsigned sx_max_export_size;
716 unsigned sx_max_export_pos_size;
717 unsigned sx_max_export_smx_size;
718 unsigned sq_num_cf_insts;
719 unsigned sx_num_of_sets;
720 unsigned sc_prim_fifo_size;
721 unsigned sc_hiz_tile_fifo_size;
722 unsigned sc_earlyz_tile_fifo_fize;
814};
815
816struct rv770_asic {
817 unsigned max_pipes;
818 unsigned max_tile_pipes;
819 unsigned max_simds;
820 unsigned max_backends;
821 unsigned max_gprs;

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826 unsigned sx_max_export_size;
827 unsigned sx_max_export_pos_size;
828 unsigned sx_max_export_smx_size;
829 unsigned sq_num_cf_insts;
830 unsigned sx_num_of_sets;
831 unsigned sc_prim_fifo_size;
832 unsigned sc_hiz_tile_fifo_size;
833 unsigned sc_earlyz_tile_fifo_fize;
834 unsigned tiling_nbanks;
835 unsigned tiling_npipes;
836 unsigned tiling_group_size;
723};
724
725union radeon_asic_config {
726 struct r300_asic r300;
727 struct r100_asic r100;
728 struct r600_asic r600;
729 struct rv770_asic rv770;
730};

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824 const struct firmware *me_fw; /* all family ME firmware */
825 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
826 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
827 struct r600_blit r600_blit;
828 int msi_enabled; /* msi enabled */
829 struct r600_ih ih; /* r6/700 interrupt ring */
830 struct workqueue_struct *wq;
831 struct work_struct hotplug_work;
837};
838
839union radeon_asic_config {
840 struct r300_asic r300;
841 struct r100_asic r100;
842 struct r600_asic r600;
843 struct rv770_asic rv770;
844};

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938 const struct firmware *me_fw; /* all family ME firmware */
939 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
940 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
941 struct r600_blit r600_blit;
942 int msi_enabled; /* msi enabled */
943 struct r600_ih ih; /* r6/700 interrupt ring */
944 struct workqueue_struct *wq;
945 struct work_struct hotplug_work;
946 int num_crtc; /* number of crtcs */
947 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
832
833 /* audio stuff */
834 struct timer_list audio_timer;
835 int audio_channels;
836 int audio_rate;
837 int audio_bits_per_sample;
838 uint8_t audio_status_bits;
839 uint8_t audio_category_code;

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950 (rdev->family == CHIP_R420) || \
951 (rdev->family == CHIP_R423) || \
952 (rdev->family == CHIP_RV410) || \
953 (rdev->family == CHIP_RS400) || \
954 (rdev->family == CHIP_RS480))
955#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
956#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
957#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
948
949 /* audio stuff */
950 struct timer_list audio_timer;
951 int audio_channels;
952 int audio_rate;
953 int audio_bits_per_sample;
954 uint8_t audio_status_bits;
955 uint8_t audio_category_code;

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1066 (rdev->family == CHIP_R420) || \
1067 (rdev->family == CHIP_R423) || \
1068 (rdev->family == CHIP_RV410) || \
1069 (rdev->family == CHIP_RS400) || \
1070 (rdev->family == CHIP_RS480))
1071#define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1072#define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1073#define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1074#define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
958
1075
959
960/*
961 * BIOS helpers.
962 */
963#define RBIOS8(i) (rdev->bios[i])
964#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
965#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
966
967int radeon_combios_init(struct radeon_device *rdev);

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1009#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1010#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1011#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1012#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1013#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1014#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1015#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1016#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1076/*
1077 * BIOS helpers.
1078 */
1079#define RBIOS8(i) (rdev->bios[i])
1080#define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1081#define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1082
1083int radeon_combios_init(struct radeon_device *rdev);

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1125#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1126#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1127#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1128#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1129#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1130#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1131#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1132#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1133#define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1017#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1018#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1019#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1020#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1021#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1022#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1023#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1024#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))

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1183extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1184extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1185 int channels,
1186 int rate,
1187 int bps,
1188 uint8_t status_bits,
1189 uint8_t category_code);
1190
1134#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1135#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1136#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1137#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1138#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1139#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1140#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1141#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))

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1300extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1301extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder,
1302 int channels,
1303 int rate,
1304 int bps,
1305 uint8_t status_bits,
1306 uint8_t category_code);
1307
1308/* evergreen */
1309struct evergreen_mc_save {
1310 u32 vga_control[6];
1311 u32 vga_render_control;
1312 u32 vga_hdp_control;
1313 u32 crtc_control[6];
1314};
1315
1191#include "radeon_object.h"
1192
1193#endif
1316#include "radeon_object.h"
1317
1318#endif