r600.c (ba4b60e85d6c5fc2242fd24e131a47fb922e5d89) r600.c (ff212f25feb44a915ce9c0144faef7fae27a6e61)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 1734 unchanged lines hidden (view full) ---

1743 */
1744bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1745{
1746 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1747
1748 if (!(reset_mask & (RADEON_RESET_GFX |
1749 RADEON_RESET_COMPUTE |
1750 RADEON_RESET_CP))) {
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 1734 unchanged lines hidden (view full) ---

1743 */
1744bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
1745{
1746 u32 reset_mask = r600_gpu_check_soft_reset(rdev);
1747
1748 if (!(reset_mask & (RADEON_RESET_GFX |
1749 RADEON_RESET_COMPUTE |
1750 RADEON_RESET_CP))) {
1751 radeon_ring_lockup_update(ring);
1751 radeon_ring_lockup_update(rdev, ring);
1752 return false;
1753 }
1754 /* force CP activities */
1755 radeon_ring_force_activity(rdev, ring);
1756 return radeon_ring_test_lockup(rdev, ring);
1757}
1758
1759u32 r6xx_remap_render_backend(struct radeon_device *rdev,

--- 839 unchanged lines hidden (view full) ---

2599 }
2600
2601 mdelay(1);
2602 WREG32(CP_RB_CNTL, tmp);
2603
2604 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2605 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2606
1752 return false;
1753 }
1754 /* force CP activities */
1755 radeon_ring_force_activity(rdev, ring);
1756 return radeon_ring_test_lockup(rdev, ring);
1757}
1758
1759u32 r6xx_remap_render_backend(struct radeon_device *rdev,

--- 839 unchanged lines hidden (view full) ---

2599 }
2600
2601 mdelay(1);
2602 WREG32(CP_RB_CNTL, tmp);
2603
2604 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2605 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2606
2607 ring->rptr = RREG32(CP_RB_RPTR);
2608
2609 r600_cp_start(rdev);
2610 ring->ready = true;
2611 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2612 if (r) {
2613 ring->ready = false;
2614 return r;
2615 }
2616

--- 1716 unchanged lines hidden --- 		2607 r600_cp_start(rdev);
2608 ring->ready = true;
2609 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2610 if (r) {
2611 ring->ready = false;
2612 return r;
2613 }
2614

--- 1716 unchanged lines hidden ---