r520.c (ec208491936d6adb8a70c3dd4a517cdfe54e823d) r520.c (550e2d9270e2f0a10c3b063899f70e4cca25fe72)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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180 /* Initialize GART (initialize after TTM so we can allocate
181 * memory through TTM but finalize after TTM) */
182 if (rdev->flags & RADEON_IS_PCIE) {
183 r = rv370_pcie_gart_enable(rdev);
184 if (r)
185 return r;
186 }
187 /* Enable IRQ */
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 171 unchanged lines hidden (view full) ---

180 /* Initialize GART (initialize after TTM so we can allocate
181 * memory through TTM but finalize after TTM) */
182 if (rdev->flags & RADEON_IS_PCIE) {
183 r = rv370_pcie_gart_enable(rdev);
184 if (r)
185 return r;
186 }
187 /* Enable IRQ */
188 rdev->irq.sw_int = true;
189 rs600_irq_set(rdev);
190 /* 1M ring buffer */
191 r = r100_cp_init(rdev, 1024 * 1024);
192 if (r) {
193 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
194 return r;
195 }
196 r = r100_wb_init(rdev);

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216 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
217 RREG32(R_000E40_RBBM_STATUS),
218 RREG32(R_0007C0_CP_STAT));
219 }
220 /* post */
221 atom_asic_init(rdev->mode_info.atom_context);
222 /* Resume clock after posting */
223 rv515_clock_startup(rdev);
188 rs600_irq_set(rdev);
189 /* 1M ring buffer */
190 r = r100_cp_init(rdev, 1024 * 1024);
191 if (r) {
192 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
193 return r;
194 }
195 r = r100_wb_init(rdev);

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215 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
216 RREG32(R_000E40_RBBM_STATUS),
217 RREG32(R_0007C0_CP_STAT));
218 }
219 /* post */
220 atom_asic_init(rdev->mode_info.atom_context);
221 /* Resume clock after posting */
222 rv515_clock_startup(rdev);
223 /* Initialize surface registers */
224 radeon_surface_init(rdev);
224 return r520_startup(rdev);
225}
226
227int r520_init(struct radeon_device *rdev)
228{
229 int r;
230
231 /* Initialize scratch registers */

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249 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
250 if (radeon_gpu_reset(rdev)) {
251 dev_warn(rdev->dev,
252 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
253 RREG32(R_000E40_RBBM_STATUS),
254 RREG32(R_0007C0_CP_STAT));
255 }
256 /* check if cards are posted or not */
225 return r520_startup(rdev);
226}
227
228int r520_init(struct radeon_device *rdev)
229{
230 int r;
231
232 /* Initialize scratch registers */

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250 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
251 if (radeon_gpu_reset(rdev)) {
252 dev_warn(rdev->dev,
253 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
254 RREG32(R_000E40_RBBM_STATUS),
255 RREG32(R_0007C0_CP_STAT));
256 }
257 /* check if cards are posted or not */
258 if (radeon_boot_test_post_card(rdev) == false)
259 return -EINVAL;
260
257 if (!radeon_card_posted(rdev) && rdev->bios) {
258 DRM_INFO("GPU not posted. posting now...\n");
259 atom_asic_init(rdev->mode_info.atom_context);
260 }
261 /* Initialize clocks */
262 radeon_get_clock_info(rdev->ddev);
263 /* Initialize power management */
264 radeon_pm_init(rdev);

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272 /* Fence driver */
273 r = radeon_fence_driver_init(rdev);
274 if (r)
275 return r;
276 r = radeon_irq_kms_init(rdev);
277 if (r)
278 return r;
279 /* Memory manager */
261 if (!radeon_card_posted(rdev) && rdev->bios) {
262 DRM_INFO("GPU not posted. posting now...\n");
263 atom_asic_init(rdev->mode_info.atom_context);
264 }
265 /* Initialize clocks */
266 radeon_get_clock_info(rdev->ddev);
267 /* Initialize power management */
268 radeon_pm_init(rdev);

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276 /* Fence driver */
277 r = radeon_fence_driver_init(rdev);
278 if (r)
279 return r;
280 r = radeon_irq_kms_init(rdev);
281 if (r)
282 return r;
283 /* Memory manager */
280 r = radeon_object_init(rdev);
284 r = radeon_bo_init(rdev);
281 if (r)
282 return r;
283 r = rv370_pcie_gart_init(rdev);
284 if (r)
285 return r;
286 rv515_set_safe_registers(rdev);
287 rdev->accel_working = true;
288 r = r520_startup(rdev);

--- 14 unchanged lines hidden --- 		285 if (r)
286 return r;
287 r = rv370_pcie_gart_init(rdev);
288 if (r)
289 return r;
290 rv515_set_safe_registers(rdev);
291 rdev->accel_working = true;
292 r = r520_startup(rdev);

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