r420.c (5958eed76ccc8c361f872829bdc4b8c6dc9cd379) r420.c (62cdc0c20663ef840a94850892517b2b7f584904)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "radeon_reg.h"
31#include "radeon.h"
32#include "atom.h"
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/seq_file.h>
29#include "drmP.h"
30#include "radeon_reg.h"
31#include "radeon.h"
32#include "atom.h"
33#include "r100d.h"
33#include "r420d.h"
34
35int r420_mc_init(struct radeon_device *rdev)
36{
37 int r;
38
39 /* Setup GPU memory space */
40 rdev->mc.vram_location = 0xFFFFFFFFUL;

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160 radeon_atom_set_clock_gating(rdev, 1);
161 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
162 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
163 if (rdev->family == CHIP_R420)
164 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
165 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
166}
167
34#include "r420d.h"
35
36int r420_mc_init(struct radeon_device *rdev)
37{
38 int r;
39
40 /* Setup GPU memory space */
41 rdev->mc.vram_location = 0xFFFFFFFFUL;

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161 radeon_atom_set_clock_gating(rdev, 1);
162 sclk_cntl = RREG32_PLL(R_00000D_SCLK_CNTL);
163 sclk_cntl |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
164 if (rdev->family == CHIP_R420)
165 sclk_cntl |= S_00000D_FORCE_PX(1) | S_00000D_FORCE_TX(1);
166 WREG32_PLL(R_00000D_SCLK_CNTL, sclk_cntl);
167}
168
169static void r420_cp_errata_init(struct radeon_device *rdev)
170{
171 /* RV410 and R420 can lock up if CP DMA to host memory happens
172 * while the 2D engine is busy.
173 *
174 * The proper workaround is to queue a RESYNC at the beginning
175 * of the CP init, apparently.
176 */
177 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
178 radeon_ring_lock(rdev, 8);
179 radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1));
180 radeon_ring_write(rdev, rdev->config.r300.resync_scratch);
181 radeon_ring_write(rdev, 0xDEADBEEF);
182 radeon_ring_unlock_commit(rdev);
183}
184
185static void r420_cp_errata_fini(struct radeon_device *rdev)
186{
187 /* Catch the RESYNC we dispatched all the way back,
188 * at the very beginning of the CP init.
189 */
190 radeon_ring_lock(rdev, 8);
191 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
192 radeon_ring_write(rdev, R300_RB3D_DC_FINISH);
193 radeon_ring_unlock_commit(rdev);
194 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
195}
196
168static int r420_startup(struct radeon_device *rdev)
169{
170 int r;
171
172 /* set common regs */
173 r100_set_common_regs(rdev);
174 /* program mc */
175 r300_mc_program(rdev);

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191 /* Enable IRQ */
192 r100_irq_set(rdev);
193 /* 1M ring buffer */
194 r = r100_cp_init(rdev, 1024 * 1024);
195 if (r) {
196 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
197 return r;
198 }
197static int r420_startup(struct radeon_device *rdev)
198{
199 int r;
200
201 /* set common regs */
202 r100_set_common_regs(rdev);
203 /* program mc */
204 r300_mc_program(rdev);

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220 /* Enable IRQ */
221 r100_irq_set(rdev);
222 /* 1M ring buffer */
223 r = r100_cp_init(rdev, 1024 * 1024);
224 if (r) {
225 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
226 return r;
227 }
228 r420_cp_errata_init(rdev);
199 r = r100_wb_init(rdev);
200 if (r) {
201 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
202 }
203 r = r100_ib_init(rdev);
204 if (r) {
205 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
206 return r;

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233 r420_clock_resume(rdev);
234 /* Initialize surface registers */
235 radeon_surface_init(rdev);
236 return r420_startup(rdev);
237}
238
239int r420_suspend(struct radeon_device *rdev)
240{
229 r = r100_wb_init(rdev);
230 if (r) {
231 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
232 }
233 r = r100_ib_init(rdev);
234 if (r) {
235 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
236 return r;

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263 r420_clock_resume(rdev);
264 /* Initialize surface registers */
265 radeon_surface_init(rdev);
266 return r420_startup(rdev);
267}
268
269int r420_suspend(struct radeon_device *rdev)
270{
271 r420_cp_errata_fini(rdev);
241 r100_cp_disable(rdev);
242 r100_wb_disable(rdev);
243 r100_irq_disable(rdev);
244 if (rdev->flags & RADEON_IS_PCIE)
245 rv370_pcie_gart_disable(rdev);
246 if (rdev->flags & RADEON_IS_PCI)
247 r100_pci_gart_disable(rdev);
248 return 0;

--- 154 unchanged lines hidden --- 		272 r100_cp_disable(rdev);
273 r100_wb_disable(rdev);
274 r100_irq_disable(rdev);
275 if (rdev->flags & RADEON_IS_PCIE)
276 rv370_pcie_gart_disable(rdev);
277 if (rdev->flags & RADEON_IS_PCI)
278 r100_pci_gart_disable(rdev);
279 return 0;

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