r200.c (e4da3fbfbd1de56d2367653e3823e6445e49f8a9) r200.c (7b1f2485db253aaa0081e1c5213533e166130732)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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82}
83
84int r200_copy_dma(struct radeon_device *rdev,
85 uint64_t src_offset,
86 uint64_t dst_offset,
87 unsigned num_gpu_pages,
88 struct radeon_fence *fence)
89{
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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82}
83
84int r200_copy_dma(struct radeon_device *rdev,
85 uint64_t src_offset,
86 uint64_t dst_offset,
87 unsigned num_gpu_pages,
88 struct radeon_fence *fence)
89{
90 struct radeon_cp *cp = &rdev->cp;
90 uint32_t size;
91 uint32_t cur_size;
92 int i, num_loops;
93 int r = 0;
94
95 /* radeon pitch is /64 */
96 size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT;
97 num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
91 uint32_t size;
92 uint32_t cur_size;
93 int i, num_loops;
94 int r = 0;
95
96 /* radeon pitch is /64 */
97 size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT;
98 num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
98 r = radeon_ring_lock(rdev, num_loops * 4 + 64);
99 r = radeon_ring_lock(rdev, cp, num_loops * 4 + 64);
99 if (r) {
100 DRM_ERROR("radeon: moving bo (%d).\n", r);
101 return r;
102 }
103 /* Must wait for 2D idle & clean before DMA or hangs might happen */
100 if (r) {
101 DRM_ERROR("radeon: moving bo (%d).\n", r);
102 return r;
103 }
104 /* Must wait for 2D idle & clean before DMA or hangs might happen */
104 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
105 radeon_ring_write(rdev, (1 << 16));
105 radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
106 radeon_ring_write(cp, (1 << 16));
106 for (i = 0; i < num_loops; i++) {
107 cur_size = size;
108 if (cur_size > 0x1FFFFF) {
109 cur_size = 0x1FFFFF;
110 }
111 size -= cur_size;
107 for (i = 0; i < num_loops; i++) {
108 cur_size = size;
109 if (cur_size > 0x1FFFFF) {
110 cur_size = 0x1FFFFF;
111 }
112 size -= cur_size;
112 radeon_ring_write(rdev, PACKET0(0x720, 2));
113 radeon_ring_write(rdev, src_offset);
114 radeon_ring_write(rdev, dst_offset);
115 radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
113 radeon_ring_write(cp, PACKET0(0x720, 2));
114 radeon_ring_write(cp, src_offset);
115 radeon_ring_write(cp, dst_offset);
116 radeon_ring_write(cp, cur_size | (1 << 31) | (1 << 30));
116 src_offset += cur_size;
117 dst_offset += cur_size;
118 }
117 src_offset += cur_size;
118 dst_offset += cur_size;
119 }
119 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
120 radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
120 radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
121 radeon_ring_write(cp, RADEON_WAIT_DMA_GUI_IDLE);
121 if (fence) {
122 r = radeon_fence_emit(rdev, fence);
123 }
122 if (fence) {
123 r = radeon_fence_emit(rdev, fence);
124 }
124 radeon_ring_unlock_commit(rdev);
125 radeon_ring_unlock_commit(rdev, cp);
125 return r;
126}
127
128
129static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)
130{
131 int vtx_size, i, tex_size;
132 vtx_size = 0;

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127}
128
129
130static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)
131{
132 int vtx_size, i, tex_size;
133 vtx_size = 0;

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