r100.c (2739d49cd7f1f44876cad614b072da698967b370) r100.c (4612dc97991a09e1a9e4d5d981e16589d7cb150c)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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361{
362 /* We have to make sure that caches are flushed before
363 * CPU might read something from VRAM. */
364 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
365 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
366 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
367 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
368 /* Wait until IDLE & CLEAN */
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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361{
362 /* We have to make sure that caches are flushed before
363 * CPU might read something from VRAM. */
364 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
365 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
366 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
367 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
368 /* Wait until IDLE & CLEAN */
369 radeon_ring_write(rdev, PACKET0(0x1720, 0));
370 radeon_ring_write(rdev, (1 << 16) | (1 << 17));
369 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
370 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
371 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
372 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
373 RADEON_HDP_READ_BUFFER_INVALIDATE);
374 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
375 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
376 /* Emit fence sequence & fire IRQ */
377 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
378 radeon_ring_write(rdev, fence->seq);

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1696 uint32_t tmp;
1697
1698 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1699 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1700 " Bad things might happen.\n");
1701 }
1702 for (i = 0; i < rdev->usec_timeout; i++) {
1703 tmp = RREG32(RADEON_RBBM_STATUS);
371 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
372 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
373 RADEON_HDP_READ_BUFFER_INVALIDATE);
374 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
375 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
376 /* Emit fence sequence & fire IRQ */
377 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
378 radeon_ring_write(rdev, fence->seq);

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1696 uint32_t tmp;
1697
1698 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1699 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1700 " Bad things might happen.\n");
1701 }
1702 for (i = 0; i < rdev->usec_timeout; i++) {
1703 tmp = RREG32(RADEON_RBBM_STATUS);
1704 if (!(tmp & (1 << 31))) {
1704 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1705 return 0;
1706 }
1707 DRM_UDELAY(1);
1708 }
1709 return -1;
1710}
1711
1712int r100_mc_wait_for_idle(struct radeon_device *rdev)
1713{
1714 unsigned i;
1715 uint32_t tmp;
1716
1717 for (i = 0; i < rdev->usec_timeout; i++) {
1718 /* read MC_STATUS */
1705 return 0;
1706 }
1707 DRM_UDELAY(1);
1708 }
1709 return -1;
1710}
1711
1712int r100_mc_wait_for_idle(struct radeon_device *rdev)
1713{
1714 unsigned i;
1715 uint32_t tmp;
1716
1717 for (i = 0; i < rdev->usec_timeout; i++) {
1718 /* read MC_STATUS */
1719 tmp = RREG32(0x0150);
1720 if (tmp & (1 << 2)) {
1719 tmp = RREG32(RADEON_MC_STATUS);
1720 if (tmp & RADEON_MC_IDLE) {
1721 return 0;
1722 }
1723 DRM_UDELAY(1);
1724 }
1725 return -1;
1726}
1727
1728void r100_gpu_init(struct radeon_device *rdev)

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1785 /* TODO: reset 3D engine */
1786 /* reset CP */
1787 status = RREG32(RADEON_RBBM_STATUS);
1788 if (status & (1 << 16)) {
1789 r100_cp_reset(rdev);
1790 }
1791 /* Check if GPU is idle */
1792 status = RREG32(RADEON_RBBM_STATUS);
1721 return 0;
1722 }
1723 DRM_UDELAY(1);
1724 }
1725 return -1;
1726}
1727
1728void r100_gpu_init(struct radeon_device *rdev)

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1785 /* TODO: reset 3D engine */
1786 /* reset CP */
1787 status = RREG32(RADEON_RBBM_STATUS);
1788 if (status & (1 << 16)) {
1789 r100_cp_reset(rdev);
1790 }
1791 /* Check if GPU is idle */
1792 status = RREG32(RADEON_RBBM_STATUS);
1793 if (status & (1 << 31)) {
1793 if (status & RADEON_RBBM_ACTIVE) {
1794 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1795 return -1;
1796 }
1797 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1798 return 0;
1799}
1800
1801void r100_set_common_regs(struct radeon_device *rdev)

--- 1762 unchanged lines hidden --- 		1794 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1795 return -1;
1796 }
1797 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1798 return 0;
1799}
1800
1801void r100_set_common_regs(struct radeon_device *rdev)

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