r100.c (15d3332f31afd571a6d23971dbc8d8db2856e661) r100.c (7b1f2485db253aaa0081e1c5213533e166130732)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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806 return RREG32(RADEON_CRTC2_CRNT_FRAME);
807}
808
809/* Who ever call radeon_fence_emit should call ring_lock and ask
810 * for enough space (today caller are ib schedule and buffer move) */
811void r100_fence_ring_emit(struct radeon_device *rdev,
812 struct radeon_fence *fence)
813{
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

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806 return RREG32(RADEON_CRTC2_CRNT_FRAME);
807}
808
809/* Who ever call radeon_fence_emit should call ring_lock and ask
810 * for enough space (today caller are ib schedule and buffer move) */
811void r100_fence_ring_emit(struct radeon_device *rdev,
812 struct radeon_fence *fence)
813{
814 struct radeon_cp *cp = &rdev->cp;
815
814 /* We have to make sure that caches are flushed before
815 * CPU might read something from VRAM. */
816 /* We have to make sure that caches are flushed before
817 * CPU might read something from VRAM. */
816 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
817 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
818 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
819 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
818 radeon_ring_write(cp, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
819 radeon_ring_write(cp, RADEON_RB3D_DC_FLUSH_ALL);
820 radeon_ring_write(cp, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
821 radeon_ring_write(cp, RADEON_RB3D_ZC_FLUSH_ALL);
820 /* Wait until IDLE & CLEAN */
822 /* Wait until IDLE & CLEAN */
821 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
822 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
823 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
824 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
823 radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
824 radeon_ring_write(cp, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
825 radeon_ring_write(cp, PACKET0(RADEON_HOST_PATH_CNTL, 0));
826 radeon_ring_write(cp, rdev->config.r100.hdp_cntl |
825 RADEON_HDP_READ_BUFFER_INVALIDATE);
827 RADEON_HDP_READ_BUFFER_INVALIDATE);
826 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
827 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
828 radeon_ring_write(cp, PACKET0(RADEON_HOST_PATH_CNTL, 0));
829 radeon_ring_write(cp, rdev->config.r100.hdp_cntl);
828 /* Emit fence sequence & fire IRQ */
830 /* Emit fence sequence & fire IRQ */
829 radeon_ring_write(rdev, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
830 radeon_ring_write(rdev, fence->seq);
831 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
832 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
831 radeon_ring_write(cp, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
832 radeon_ring_write(cp, fence->seq);
833 radeon_ring_write(cp, PACKET0(RADEON_GEN_INT_STATUS, 0));
834 radeon_ring_write(cp, RADEON_SW_INT_FIRE);
833}
834
835void r100_semaphore_ring_emit(struct radeon_device *rdev,
835}
836
837void r100_semaphore_ring_emit(struct radeon_device *rdev,
838 struct radeon_cp *cp,
836 struct radeon_semaphore *semaphore,
839 struct radeon_semaphore *semaphore,
837 unsigned ring, bool emit_wait)
840 bool emit_wait)
838{
839 /* Unused on older asics, since we don't have semaphores or multiple rings */
840 BUG();
841}
842
843int r100_copy_blit(struct radeon_device *rdev,
844 uint64_t src_offset,
845 uint64_t dst_offset,
846 unsigned num_gpu_pages,
847 struct radeon_fence *fence)
848{
841{
842 /* Unused on older asics, since we don't have semaphores or multiple rings */
843 BUG();
844}
845
846int r100_copy_blit(struct radeon_device *rdev,
847 uint64_t src_offset,
848 uint64_t dst_offset,
849 unsigned num_gpu_pages,
850 struct radeon_fence *fence)
851{
852 struct radeon_cp *cp = &rdev->cp;
849 uint32_t cur_pages;
850 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
851 uint32_t pitch;
852 uint32_t stride_pixels;
853 unsigned ndw;
854 int num_loops;
855 int r = 0;
856
857 /* radeon limited to 16k stride */
858 stride_bytes &= 0x3fff;
859 /* radeon pitch is /64 */
860 pitch = stride_bytes / 64;
861 stride_pixels = stride_bytes / 4;
862 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
863
864 /* Ask for enough room for blit + flush + fence */
865 ndw = 64 + (10 * num_loops);
853 uint32_t cur_pages;
854 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
855 uint32_t pitch;
856 uint32_t stride_pixels;
857 unsigned ndw;
858 int num_loops;
859 int r = 0;
860
861 /* radeon limited to 16k stride */
862 stride_bytes &= 0x3fff;
863 /* radeon pitch is /64 */
864 pitch = stride_bytes / 64;
865 stride_pixels = stride_bytes / 4;
866 num_loops = DIV_ROUND_UP(num_gpu_pages, 8191);
867
868 /* Ask for enough room for blit + flush + fence */
869 ndw = 64 + (10 * num_loops);
866 r = radeon_ring_lock(rdev, ndw);
870 r = radeon_ring_lock(rdev, cp, ndw);
867 if (r) {
868 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
869 return -EINVAL;
870 }
871 while (num_gpu_pages > 0) {
872 cur_pages = num_gpu_pages;
873 if (cur_pages > 8191) {
874 cur_pages = 8191;
875 }
876 num_gpu_pages -= cur_pages;
877
878 /* pages are in Y direction - height
879 page width in X direction - width */
871 if (r) {
872 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
873 return -EINVAL;
874 }
875 while (num_gpu_pages > 0) {
876 cur_pages = num_gpu_pages;
877 if (cur_pages > 8191) {
878 cur_pages = 8191;
879 }
880 num_gpu_pages -= cur_pages;
881
882 /* pages are in Y direction - height
883 page width in X direction - width */
880 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
881 radeon_ring_write(rdev,
884 radeon_ring_write(cp, PACKET3(PACKET3_BITBLT_MULTI, 8));
885 radeon_ring_write(cp,
882 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
883 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
884 RADEON_GMC_SRC_CLIPPING |
885 RADEON_GMC_DST_CLIPPING |
886 RADEON_GMC_BRUSH_NONE |
887 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
888 RADEON_GMC_SRC_DATATYPE_COLOR |
889 RADEON_ROP3_S |
890 RADEON_DP_SRC_SOURCE_MEMORY |
891 RADEON_GMC_CLR_CMP_CNTL_DIS |
892 RADEON_GMC_WR_MSK_DIS);
886 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
887 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
888 RADEON_GMC_SRC_CLIPPING |
889 RADEON_GMC_DST_CLIPPING |
890 RADEON_GMC_BRUSH_NONE |
891 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
892 RADEON_GMC_SRC_DATATYPE_COLOR |
893 RADEON_ROP3_S |
894 RADEON_DP_SRC_SOURCE_MEMORY |
895 RADEON_GMC_CLR_CMP_CNTL_DIS |
896 RADEON_GMC_WR_MSK_DIS);
893 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
894 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
895 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
896 radeon_ring_write(rdev, 0);
897 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
898 radeon_ring_write(rdev, num_gpu_pages);
899 radeon_ring_write(rdev, num_gpu_pages);
900 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
897 radeon_ring_write(cp, (pitch << 22) | (src_offset >> 10));
898 radeon_ring_write(cp, (pitch << 22) | (dst_offset >> 10));
899 radeon_ring_write(cp, (0x1fff) | (0x1fff << 16));
900 radeon_ring_write(cp, 0);
901 radeon_ring_write(cp, (0x1fff) | (0x1fff << 16));
902 radeon_ring_write(cp, num_gpu_pages);
903 radeon_ring_write(cp, num_gpu_pages);
904 radeon_ring_write(cp, cur_pages | (stride_pixels << 16));
901 }
905 }
902 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
903 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
904 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
905 radeon_ring_write(rdev,
906 radeon_ring_write(cp, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
907 radeon_ring_write(cp, RADEON_RB2D_DC_FLUSH_ALL);
908 radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
909 radeon_ring_write(cp,
906 RADEON_WAIT_2D_IDLECLEAN |
907 RADEON_WAIT_HOST_IDLECLEAN |
908 RADEON_WAIT_DMA_GUI_IDLE);
909 if (fence) {
910 r = radeon_fence_emit(rdev, fence);
911 }
910 RADEON_WAIT_2D_IDLECLEAN |
911 RADEON_WAIT_HOST_IDLECLEAN |
912 RADEON_WAIT_DMA_GUI_IDLE);
913 if (fence) {
914 r = radeon_fence_emit(rdev, fence);
915 }
912 radeon_ring_unlock_commit(rdev);
916 radeon_ring_unlock_commit(rdev, cp);
913 return r;
914}
915
916static int r100_cp_wait_for_idle(struct radeon_device *rdev)
917{
918 unsigned i;
919 u32 tmp;
920

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925 }
926 udelay(1);
927 }
928 return -1;
929}
930
931void r100_ring_start(struct radeon_device *rdev)
932{
917 return r;
918}
919
920static int r100_cp_wait_for_idle(struct radeon_device *rdev)
921{
922 unsigned i;
923 u32 tmp;
924

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929 }
930 udelay(1);
931 }
932 return -1;
933}
934
935void r100_ring_start(struct radeon_device *rdev)
936{
937 struct radeon_cp *cp = &rdev->cp;
933 int r;
934
938 int r;
939
935 r = radeon_ring_lock(rdev, 2);
940 r = radeon_ring_lock(rdev, cp, 2);
936 if (r) {
937 return;
938 }
941 if (r) {
942 return;
943 }
939 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
940 radeon_ring_write(rdev,
944 radeon_ring_write(cp, PACKET0(RADEON_ISYNC_CNTL, 0));
945 radeon_ring_write(cp,
941 RADEON_ISYNC_ANY2D_IDLE3D |
942 RADEON_ISYNC_ANY3D_IDLE2D |
943 RADEON_ISYNC_WAIT_IDLEGUI |
944 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
946 RADEON_ISYNC_ANY2D_IDLE3D |
947 RADEON_ISYNC_ANY3D_IDLE2D |
948 RADEON_ISYNC_WAIT_IDLEGUI |
949 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
945 radeon_ring_unlock_commit(rdev);
950 radeon_ring_unlock_commit(rdev, cp);
946}
947
948
949/* Load the microcode for the CP */
950static int r100_cp_init_microcode(struct radeon_device *rdev)
951{
952 struct platform_device *pdev;
953 const char *fw_name = NULL;

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1038 WREG32(RADEON_CP_ME_RAM_DATAL,
1039 be32_to_cpup(&fw_data[i + 1]));
1040 }
1041 }
1042}
1043
1044int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1045{
951}
952
953
954/* Load the microcode for the CP */
955static int r100_cp_init_microcode(struct radeon_device *rdev)
956{
957 struct platform_device *pdev;
958 const char *fw_name = NULL;

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1043 WREG32(RADEON_CP_ME_RAM_DATAL,
1044 be32_to_cpup(&fw_data[i + 1]));
1045 }
1046 }
1047}
1048
1049int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1050{
1051 struct radeon_cp *cp = &rdev->cp;
1046 unsigned rb_bufsz;
1047 unsigned rb_blksz;
1048 unsigned max_fetch;
1049 unsigned pre_write_timer;
1050 unsigned pre_write_limit;
1051 unsigned indirect2_start;
1052 unsigned indirect1_start;
1053 uint32_t tmp;

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1063 return r;
1064 }
1065 }
1066
1067 /* Align ring size */
1068 rb_bufsz = drm_order(ring_size / 8);
1069 ring_size = (1 << (rb_bufsz + 1)) * 4;
1070 r100_cp_load_microcode(rdev);
1052 unsigned rb_bufsz;
1053 unsigned rb_blksz;
1054 unsigned max_fetch;
1055 unsigned pre_write_timer;
1056 unsigned pre_write_limit;
1057 unsigned indirect2_start;
1058 unsigned indirect1_start;
1059 uint32_t tmp;

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1069 return r;
1070 }
1071 }
1072
1073 /* Align ring size */
1074 rb_bufsz = drm_order(ring_size / 8);
1075 ring_size = (1 << (rb_bufsz + 1)) * 4;
1076 r100_cp_load_microcode(rdev);
1071 r = radeon_ring_init(rdev, ring_size);
1077 r = radeon_ring_init(rdev, cp, ring_size);
1072 if (r) {
1073 return r;
1074 }
1075 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1076 * the rptr copy in system ram */
1077 rb_blksz = 9;
1078 /* cp will read 128bytes at a time (4 dwords) */
1079 max_fetch = 1;
1078 if (r) {
1079 return r;
1080 }
1081 /* Each time the cp read 1024 bytes (16 dword/quadword) update
1082 * the rptr copy in system ram */
1083 rb_blksz = 9;
1084 /* cp will read 128bytes at a time (4 dwords) */
1085 max_fetch = 1;
1080 rdev->cp.align_mask = 16 - 1;
1086 cp->align_mask = 16 - 1;
1081 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1082 pre_write_timer = 64;
1083 /* Force CP_RB_WPTR write if written more than one time before the
1084 * delay expire
1085 */
1086 pre_write_limit = 0;
1087 /* Setup the cp cache like this (cache size is 96 dwords) :
1088 * RING 0 to 15

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1102 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1103 REG_SET(RADEON_MAX_FETCH, max_fetch));
1104#ifdef __BIG_ENDIAN
1105 tmp |= RADEON_BUF_SWAP_32BIT;
1106#endif
1107 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1108
1109 /* Set ring address */
1087 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1088 pre_write_timer = 64;
1089 /* Force CP_RB_WPTR write if written more than one time before the
1090 * delay expire
1091 */
1092 pre_write_limit = 0;
1093 /* Setup the cp cache like this (cache size is 96 dwords) :
1094 * RING 0 to 15

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1108 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
1109 REG_SET(RADEON_MAX_FETCH, max_fetch));
1110#ifdef __BIG_ENDIAN
1111 tmp |= RADEON_BUF_SWAP_32BIT;
1112#endif
1113 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1114
1115 /* Set ring address */
1110 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
1111 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
1116 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)cp->gpu_addr);
1117 WREG32(RADEON_CP_RB_BASE, cp->gpu_addr);
1112 /* Force read & write ptr to 0 */
1113 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1114 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1118 /* Force read & write ptr to 0 */
1119 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1120 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1115 rdev->cp.wptr = 0;
1116 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1121 cp->wptr = 0;
1122 WREG32(RADEON_CP_RB_WPTR, cp->wptr);
1117
1118 /* set the wb address whether it's enabled or not */
1119 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1120 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1121 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1122
1123 if (rdev->wb.enabled)
1124 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1125 else {
1126 tmp |= RADEON_RB_NO_UPDATE;
1127 WREG32(R_000770_SCRATCH_UMSK, 0);
1128 }
1129
1130 WREG32(RADEON_CP_RB_CNTL, tmp);
1131 udelay(10);
1123
1124 /* set the wb address whether it's enabled or not */
1125 WREG32(R_00070C_CP_RB_RPTR_ADDR,
1126 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) >> 2));
1127 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET);
1128
1129 if (rdev->wb.enabled)
1130 WREG32(R_000770_SCRATCH_UMSK, 0xff);
1131 else {
1132 tmp |= RADEON_RB_NO_UPDATE;
1133 WREG32(R_000770_SCRATCH_UMSK, 0);
1134 }
1135
1136 WREG32(RADEON_CP_RB_CNTL, tmp);
1137 udelay(10);
1132 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
1138 cp->rptr = RREG32(RADEON_CP_RB_RPTR);
1133 /* Set cp mode to bus mastering & enable cp*/
1134 WREG32(RADEON_CP_CSQ_MODE,
1135 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1136 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1137 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1138 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1139 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1140 radeon_ring_start(rdev);
1139 /* Set cp mode to bus mastering & enable cp*/
1140 WREG32(RADEON_CP_CSQ_MODE,
1141 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
1142 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
1143 WREG32(RADEON_CP_RB_WPTR_DELAY, 0);
1144 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1145 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1146 radeon_ring_start(rdev);
1141 r = radeon_ring_test(rdev);
1147 r = radeon_ring_test(rdev, cp);
1142 if (r) {
1143 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1144 return r;
1145 }
1148 if (r) {
1149 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1150 return r;
1151 }
1146 rdev->cp.ready = true;
1152 cp->ready = true;
1147 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1148 return 0;
1149}
1150
1151void r100_cp_fini(struct radeon_device *rdev)
1152{
1153 if (r100_cp_wait_for_idle(rdev)) {
1154 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1155 }
1156 /* Disable ring */
1157 r100_cp_disable(rdev);
1153 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1154 return 0;
1155}
1156
1157void r100_cp_fini(struct radeon_device *rdev)
1158{
1159 if (r100_cp_wait_for_idle(rdev)) {
1160 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
1161 }
1162 /* Disable ring */
1163 r100_cp_disable(rdev);
1158 radeon_ring_fini(rdev);
1164 radeon_ring_fini(rdev, &rdev->cp);
1159 DRM_INFO("radeon: cp finalized\n");
1160}
1161
1162void r100_cp_disable(struct radeon_device *rdev)
1163{
1164 /* Disable ring */
1165 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1166 rdev->cp.ready = false;
1167 WREG32(RADEON_CP_CSQ_MODE, 0);
1168 WREG32(RADEON_CP_CSQ_CNTL, 0);
1169 WREG32(R_000770_SCRATCH_UMSK, 0);
1170 if (r100_gui_wait_for_idle(rdev)) {
1171 printk(KERN_WARNING "Failed to wait GUI idle while "
1172 "programming pipes. Bad things might happen.\n");
1173 }
1174}
1175
1165 DRM_INFO("radeon: cp finalized\n");
1166}
1167
1168void r100_cp_disable(struct radeon_device *rdev)
1169{
1170 /* Disable ring */
1171 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1172 rdev->cp.ready = false;
1173 WREG32(RADEON_CP_CSQ_MODE, 0);
1174 WREG32(RADEON_CP_CSQ_CNTL, 0);
1175 WREG32(R_000770_SCRATCH_UMSK, 0);
1176 if (r100_gui_wait_for_idle(rdev)) {
1177 printk(KERN_WARNING "Failed to wait GUI idle while "
1178 "programming pipes. Bad things might happen.\n");
1179 }
1180}
1181
1176void r100_cp_commit(struct radeon_device *rdev)
1182void r100_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp)
1177{
1183{
1178 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
1184 WREG32(RADEON_CP_RB_WPTR, cp->wptr);
1179 (void)RREG32(RADEON_CP_RB_WPTR);
1180}
1181
1182
1183/*
1184 * CS functions
1185 */
1186int r100_cs_parse_packet0(struct radeon_cs_parser *p,

--- 968 unchanged lines hidden (view full) ---

2155 if (elapsed >= 10000) {
2156 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2157 return true;
2158 }
2159 /* give a chance to the GPU ... */
2160 return false;
2161}
2162
1185 (void)RREG32(RADEON_CP_RB_WPTR);
1186}
1187
1188
1189/*
1190 * CS functions
1191 */
1192int r100_cs_parse_packet0(struct radeon_cs_parser *p,

--- 968 unchanged lines hidden (view full) ---

2161 if (elapsed >= 10000) {
2162 dev_err(rdev->dev, "GPU lockup CP stall for more than %lumsec\n", elapsed);
2163 return true;
2164 }
2165 /* give a chance to the GPU ... */
2166 return false;
2167}
2168
2163bool r100_gpu_is_lockup(struct radeon_device *rdev)
2169bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
2164{
2165 u32 rbbm_status;
2166 int r;
2167
2168 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2169 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2170{
2171 u32 rbbm_status;
2172 int r;
2173
2174 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2175 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2170 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp);
2176 r100_gpu_lockup_update(&rdev->config.r100.lockup, cp);
2171 return false;
2172 }
2173 /* force CP activities */
2177 return false;
2178 }
2179 /* force CP activities */
2174 r = radeon_ring_lock(rdev, 2);
2180 r = radeon_ring_lock(rdev, cp, 2);
2175 if (!r) {
2176 /* PACKET2 NOP */
2181 if (!r) {
2182 /* PACKET2 NOP */
2177 radeon_ring_write(rdev, 0x80000000);
2178 radeon_ring_write(rdev, 0x80000000);
2179 radeon_ring_unlock_commit(rdev);
2183 radeon_ring_write(cp, 0x80000000);
2184 radeon_ring_write(cp, 0x80000000);
2185 radeon_ring_unlock_commit(rdev, cp);
2180 }
2186 }
2181 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
2182 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp);
2187 cp->rptr = RREG32(RADEON_CP_RB_RPTR);
2188 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, cp);
2183}
2184
2185void r100_bm_disable(struct radeon_device *rdev)
2186{
2187 u32 tmp;
2188
2189 /* disable bus mastering */
2190 tmp = RREG32(R_000030_BUS_CNTL);

--- 391 unchanged lines hidden (view full) ---

2582 return 0;
2583}
2584
2585static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2586{
2587 struct drm_info_node *node = (struct drm_info_node *) m->private;
2588 struct drm_device *dev = node->minor->dev;
2589 struct radeon_device *rdev = dev->dev_private;
2189}
2190
2191void r100_bm_disable(struct radeon_device *rdev)
2192{
2193 u32 tmp;
2194
2195 /* disable bus mastering */
2196 tmp = RREG32(R_000030_BUS_CNTL);

--- 391 unchanged lines hidden (view full) ---

2588 return 0;
2589}
2590
2591static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2592{
2593 struct drm_info_node *node = (struct drm_info_node *) m->private;
2594 struct drm_device *dev = node->minor->dev;
2595 struct radeon_device *rdev = dev->dev_private;
2596 struct radeon_cp *cp = &rdev->cp;
2590 uint32_t rdp, wdp;
2591 unsigned count, i, j;
2592
2597 uint32_t rdp, wdp;
2598 unsigned count, i, j;
2599
2593 radeon_ring_free_size(rdev);
2600 radeon_ring_free_size(rdev, cp);
2594 rdp = RREG32(RADEON_CP_RB_RPTR);
2595 wdp = RREG32(RADEON_CP_RB_WPTR);
2601 rdp = RREG32(RADEON_CP_RB_RPTR);
2602 wdp = RREG32(RADEON_CP_RB_WPTR);
2596 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2603 count = (rdp + cp->ring_size - wdp) & cp->ptr_mask;
2597 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2598 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2599 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2604 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2605 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2606 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2600 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2607 seq_printf(m, "%u free dwords in ring\n", cp->ring_free_dw);
2601 seq_printf(m, "%u dwords in ring\n", count);
2602 for (j = 0; j <= count; j++) {
2608 seq_printf(m, "%u dwords in ring\n", count);
2609 for (j = 0; j <= count; j++) {
2603 i = (rdp + j) & rdev->cp.ptr_mask;
2604 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2610 i = (rdp + j) & cp->ptr_mask;
2611 seq_printf(m, "r[%04d]=0x%08x\n", i, cp->ring[i]);
2605 }
2606 return 0;
2607}
2608
2609
2610static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2611{
2612 struct drm_info_node *node = (struct drm_info_node *) m->private;

--- 1025 unchanged lines hidden (view full) ---

3638 track->textures[i].cube_info[face].robj = NULL;
3639 track->textures[i].cube_info[face].width = 16536;
3640 track->textures[i].cube_info[face].height = 16536;
3641 track->textures[i].cube_info[face].offset = 0;
3642 }
3643 }
3644}
3645
2612 }
2613 return 0;
2614}
2615
2616
2617static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2618{
2619 struct drm_info_node *node = (struct drm_info_node *) m->private;

--- 1025 unchanged lines hidden (view full) ---

3645 track->textures[i].cube_info[face].robj = NULL;
3646 track->textures[i].cube_info[face].width = 16536;
3647 track->textures[i].cube_info[face].height = 16536;
3648 track->textures[i].cube_info[face].offset = 0;
3649 }
3650 }
3651}
3652
3646int r100_ring_test(struct radeon_device *rdev)
3653int r100_ring_test(struct radeon_device *rdev, struct radeon_cp *cp)
3647{
3648 uint32_t scratch;
3649 uint32_t tmp = 0;
3650 unsigned i;
3651 int r;
3652
3653 r = radeon_scratch_get(rdev, &scratch);
3654 if (r) {
3655 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3656 return r;
3657 }
3658 WREG32(scratch, 0xCAFEDEAD);
3654{
3655 uint32_t scratch;
3656 uint32_t tmp = 0;
3657 unsigned i;
3658 int r;
3659
3660 r = radeon_scratch_get(rdev, &scratch);
3661 if (r) {
3662 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3663 return r;
3664 }
3665 WREG32(scratch, 0xCAFEDEAD);
3659 r = radeon_ring_lock(rdev, 2);
3666 r = radeon_ring_lock(rdev, cp, 2);
3660 if (r) {
3661 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3662 radeon_scratch_free(rdev, scratch);
3663 return r;
3664 }
3667 if (r) {
3668 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3669 radeon_scratch_free(rdev, scratch);
3670 return r;
3671 }
3665 radeon_ring_write(rdev, PACKET0(scratch, 0));
3666 radeon_ring_write(rdev, 0xDEADBEEF);
3667 radeon_ring_unlock_commit(rdev);
3672 radeon_ring_write(cp, PACKET0(scratch, 0));
3673 radeon_ring_write(cp, 0xDEADBEEF);
3674 radeon_ring_unlock_commit(rdev, cp);
3668 for (i = 0; i < rdev->usec_timeout; i++) {
3669 tmp = RREG32(scratch);
3670 if (tmp == 0xDEADBEEF) {
3671 break;
3672 }
3673 DRM_UDELAY(1);
3674 }
3675 if (i < rdev->usec_timeout) {

--- 4 unchanged lines hidden (view full) ---

3680 r = -EINVAL;
3681 }
3682 radeon_scratch_free(rdev, scratch);
3683 return r;
3684}
3685
3686void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3687{
3675 for (i = 0; i < rdev->usec_timeout; i++) {
3676 tmp = RREG32(scratch);
3677 if (tmp == 0xDEADBEEF) {
3678 break;
3679 }
3680 DRM_UDELAY(1);
3681 }
3682 if (i < rdev->usec_timeout) {

--- 4 unchanged lines hidden (view full) ---

3687 r = -EINVAL;
3688 }
3689 radeon_scratch_free(rdev, scratch);
3690 return r;
3691}
3692
3693void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3694{
3688 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3689 radeon_ring_write(rdev, ib->gpu_addr);
3690 radeon_ring_write(rdev, ib->length_dw);
3695 struct radeon_cp *cp = &rdev->cp;
3696
3697 radeon_ring_write(cp, PACKET0(RADEON_CP_IB_BASE, 1));
3698 radeon_ring_write(cp, ib->gpu_addr);
3699 radeon_ring_write(cp, ib->length_dw);
3691}
3692
3693int r100_ib_test(struct radeon_device *rdev)
3694{
3695 struct radeon_ib *ib;
3696 uint32_t scratch;
3697 uint32_t tmp = 0;
3698 unsigned i;
3699 int r;
3700
3701 r = radeon_scratch_get(rdev, &scratch);
3702 if (r) {
3703 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3704 return r;
3705 }
3706 WREG32(scratch, 0xCAFEDEAD);
3700}
3701
3702int r100_ib_test(struct radeon_device *rdev)
3703{
3704 struct radeon_ib *ib;
3705 uint32_t scratch;
3706 uint32_t tmp = 0;
3707 unsigned i;
3708 int r;
3709
3710 r = radeon_scratch_get(rdev, &scratch);
3711 if (r) {
3712 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3713 return r;
3714 }
3715 WREG32(scratch, 0xCAFEDEAD);
3707 r = radeon_ib_get(rdev, &ib);
3716 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib);
3708 if (r) {
3709 return r;
3710 }
3711 ib->ptr[0] = PACKET0(scratch, 0);
3712 ib->ptr[1] = 0xDEADBEEF;
3713 ib->ptr[2] = PACKET2(0);
3714 ib->ptr[3] = PACKET2(0);
3715 ib->ptr[4] = PACKET2(0);

--- 414 unchanged lines hidden --- 		3717 if (r) {
3718 return r;
3719 }
3720 ib->ptr[0] = PACKET0(scratch, 0);
3721 ib->ptr[1] = 0xDEADBEEF;
3722 ib->ptr[2] = PACKET2(0);
3723 ib->ptr[3] = PACKET2(0);
3724 ib->ptr[4] = PACKET2(0);

--- 414 unchanged lines hidden ---