| evergreend.h (7483948fdd31a8642ef0288aab6f368b98d53c29) | evergreend.h (dd220a00e8bd5ad7f98ecdc3eed699a7cfabdc27) |
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| 1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the --- 63 unchanged lines hidden (view full) --- 72 73#define CGTS_SYS_TCC_DISABLE 0x3F90 74#define CGTS_TCC_DISABLE 0x9148 75#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 76#define CGTS_USER_TCC_DISABLE 0x914C 77 78#define CONFIG_MEMSIZE 0x5428 79 | 1/* 2 * Copyright 2010 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the --- 63 unchanged lines hidden (view full) --- 72 73#define CGTS_SYS_TCC_DISABLE 0x3F90 74#define CGTS_TCC_DISABLE 0x9148 75#define CGTS_USER_SYS_TCC_DISABLE 0x3F94 76#define CGTS_USER_TCC_DISABLE 0x914C 77 78#define CONFIG_MEMSIZE 0x5428 79 |
| 80#define CP_COHER_BASE 0x85F8 |
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| 80#define CP_ME_CNTL 0x86D8 81#define CP_ME_HALT (1 << 28) 82#define CP_PFP_HALT (1 << 26) 83#define CP_ME_RAM_DATA 0xC160 84#define CP_ME_RAM_RADDR 0xC158 85#define CP_ME_RAM_WADDR 0xC15C 86#define CP_MEQ_THRESHOLDS 0x8764 87#define STQ_SPLIT(x) ((x) << 0) --- 855 unchanged lines hidden (view full) --- 943#define SQ_PGM_START_PS 0x28840 944#define SQ_PGM_START_VS 0x2885c 945#define SQ_PGM_START_GS 0x28874 946#define SQ_PGM_START_ES 0x2888c 947#define SQ_PGM_START_FS 0x288a4 948#define SQ_PGM_START_HS 0x288b8 949#define SQ_PGM_START_LS 0x288d0 950 | 81#define CP_ME_CNTL 0x86D8 82#define CP_ME_HALT (1 << 28) 83#define CP_PFP_HALT (1 << 26) 84#define CP_ME_RAM_DATA 0xC160 85#define CP_ME_RAM_RADDR 0xC158 86#define CP_ME_RAM_WADDR 0xC15C 87#define CP_MEQ_THRESHOLDS 0x8764 88#define STQ_SPLIT(x) ((x) << 0) --- 855 unchanged lines hidden (view full) --- 944#define SQ_PGM_START_PS 0x28840 945#define SQ_PGM_START_VS 0x2885c 946#define SQ_PGM_START_GS 0x28874 947#define SQ_PGM_START_ES 0x2888c 948#define SQ_PGM_START_FS 0x288a4 949#define SQ_PGM_START_HS 0x288b8 950#define SQ_PGM_START_LS 0x288d0 951 |
| 952#define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 953#define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 954#define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 955#define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 956#define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 957#define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 958#define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 959#define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 |
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| 951#define VGT_STRMOUT_CONFIG 0x28b94 952#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 953 954#define CB_TARGET_MASK 0x28238 955#define CB_SHADER_MASK 0x2823c 956 957#define GDS_ADDR_BASE 0x28720 958 --- 307 unchanged lines hidden --- | 960#define VGT_STRMOUT_CONFIG 0x28b94 961#define VGT_STRMOUT_BUFFER_CONFIG 0x28b98 962 963#define CB_TARGET_MASK 0x28238 964#define CB_SHADER_MASK 0x2823c 965 966#define GDS_ADDR_BASE 0x28720 967 --- 307 unchanged lines hidden --- |