evergreen.c (bb51eeee5a947f61eeefaa55221c26460542654d) evergreen.c (134b480f4b92654b9590fad6c9374c7dc6722375)
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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1188 */
1189 if ((v == 0) || (v == 6) || (v == 7)) {
1190 ctl &= ~PCI_EXP_DEVCTL_READRQ;
1191 ctl |= (2 << 12);
1192 pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
1193 }
1194}
1195
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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1188 */
1189 if ((v == 0) || (v == 6) || (v == 7)) {
1190 ctl &= ~PCI_EXP_DEVCTL_READRQ;
1191 ctl |= (2 << 12);
1192 pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
1193 }
1194}
1195
1196void dce4_program_fmt(struct drm_encoder *encoder)
1197{
1198 struct drm_device *dev = encoder->dev;
1199 struct radeon_device *rdev = dev->dev_private;
1200 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1201 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1202 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1203 int bpc = 0;
1204 u32 tmp = 0;
1205 bool dither = false;
1206
1207 if (connector)
1208 bpc = radeon_get_monitor_bpc(connector);
1209
1210 /* LVDS/eDP FMT is set up by atom */
1211 if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
1212 return;
1213
1214 /* not needed for analog */
1215 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
1216 (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
1217 return;
1218
1219 if (bpc == 0)
1220 return;
1221
1222 switch (bpc) {
1223 case 6:
1224 if (dither)
1225 /* XXX sort out optimal dither settings */
1226 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
1227 FMT_SPATIAL_DITHER_EN);
1228 else
1229 tmp |= FMT_TRUNCATE_EN;
1230 break;
1231 case 8:
1232 if (dither)
1233 /* XXX sort out optimal dither settings */
1234 tmp |= (FMT_FRAME_RANDOM_ENABLE | FMT_HIGHPASS_RANDOM_ENABLE |
1235 FMT_RGB_RANDOM_ENABLE |
1236 FMT_SPATIAL_DITHER_EN | FMT_SPATIAL_DITHER_DEPTH);
1237 else
1238 tmp |= (FMT_TRUNCATE_EN | FMT_TRUNCATE_DEPTH);
1239 break;
1240 case 10:
1241 default:
1242 /* not needed */
1243 break;
1244 }
1245
1246 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp);
1247}
1248
1196static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
1197{
1198 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
1199 return true;
1200 else
1201 return false;
1202}
1203

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3126 rdev->config.evergreen.max_gprs = 256;
3127 rdev->config.evergreen.max_threads = 248;
3128 rdev->config.evergreen.max_gs_threads = 32;
3129 rdev->config.evergreen.max_stack_entries = 512;
3130 rdev->config.evergreen.sx_num_of_sets = 4;
3131 rdev->config.evergreen.sx_max_export_size = 256;
3132 rdev->config.evergreen.sx_max_export_pos_size = 64;
3133 rdev->config.evergreen.sx_max_export_smx_size = 192;
1249static bool dce4_is_in_vblank(struct radeon_device *rdev, int crtc)
1250{
1251 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
1252 return true;
1253 else
1254 return false;
1255}
1256

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3179 rdev->config.evergreen.max_gprs = 256;
3180 rdev->config.evergreen.max_threads = 248;
3181 rdev->config.evergreen.max_gs_threads = 32;
3182 rdev->config.evergreen.max_stack_entries = 512;
3183 rdev->config.evergreen.sx_num_of_sets = 4;
3184 rdev->config.evergreen.sx_max_export_size = 256;
3185 rdev->config.evergreen.sx_max_export_pos_size = 64;
3186 rdev->config.evergreen.sx_max_export_smx_size = 192;
3134 rdev->config.evergreen.max_hw_contexts = 4;
3187 rdev->config.evergreen.max_hw_contexts = 8;
3135 rdev->config.evergreen.sq_num_cf_insts = 2;
3136
3137 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3138 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3139 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3140 gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN;
3141 break;
3142 case CHIP_BARTS:

--- 2454 unchanged lines hidden --- 		3188 rdev->config.evergreen.sq_num_cf_insts = 2;
3189
3190 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
3191 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
3192 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
3193 gb_addr_config = SUMO2_GB_ADDR_CONFIG_GOLDEN;
3194 break;
3195 case CHIP_BARTS:

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