evergreen.c (3c3d7cb1db4af176dab843f22ea092a4ef1eb989) evergreen.c (ff212f25feb44a915ce9c0144faef7fae27a6e61)
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 2976 unchanged lines hidden (view full) ---

2985 }
2986
2987 mdelay(1);
2988 WREG32(CP_RB_CNTL, tmp);
2989
2990 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2991 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2992
1/*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 2976 unchanged lines hidden (view full) ---

2985 }
2986
2987 mdelay(1);
2988 WREG32(CP_RB_CNTL, tmp);
2989
2990 WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
2991 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2992
2993 ring->rptr = RREG32(CP_RB_RPTR);
2994
2995 evergreen_cp_start(rdev);
2996 ring->ready = true;
2997 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2998 if (r) {
2999 ring->ready = false;
3000 return r;
3001 }
3002 return 0;

--- 944 unchanged lines hidden (view full) ---

3947 */
3948bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
3949{
3950 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
3951
3952 if (!(reset_mask & (RADEON_RESET_GFX |
3953 RADEON_RESET_COMPUTE |
3954 RADEON_RESET_CP))) {
2993 evergreen_cp_start(rdev);
2994 ring->ready = true;
2995 r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
2996 if (r) {
2997 ring->ready = false;
2998 return r;
2999 }
3000 return 0;

--- 944 unchanged lines hidden (view full) ---

3945 */
3946bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
3947{
3948 u32 reset_mask = evergreen_gpu_check_soft_reset(rdev);
3949
3950 if (!(reset_mask & (RADEON_RESET_GFX |
3951 RADEON_RESET_COMPUTE |
3952 RADEON_RESET_CP))) {
3955 radeon_ring_lockup_update(ring);
3953 radeon_ring_lockup_update(rdev, ring);
3956 return false;
3957 }
3958 /* force CP activities */
3959 radeon_ring_force_activity(rdev, ring);
3960 return radeon_ring_test_lockup(rdev, ring);
3961}
3962
3963/*

--- 1739 unchanged lines hidden --- 		3954 return false;
3955 }
3956 /* force CP activities */
3957 radeon_ring_force_activity(rdev, ring);
3958 return radeon_ring_test_lockup(rdev, ring);
3959}
3960
3961/*

--- 1739 unchanged lines hidden ---