cmdq.c (4b4193256c8d3bc3a5397b5cd9494c2ad386317d) cmdq.c (2541626cfb794e57ba0575a6920826f591f7ced0)
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 37 unchanged lines hidden (view full) ---

46
47 return size <= free;
48}
49
50static void
51nvkm_falcon_cmdq_push(struct nvkm_falcon_cmdq *cmdq, void *data, u32 size)
52{
53 struct nvkm_falcon *falcon = cmdq->qmgr->falcon;
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 37 unchanged lines hidden (view full) ---

46
47 return size <= free;
48}
49
50static void
51nvkm_falcon_cmdq_push(struct nvkm_falcon_cmdq *cmdq, void *data, u32 size)
52{
53 struct nvkm_falcon *falcon = cmdq->qmgr->falcon;
54 nvkm_falcon_load_dmem(falcon, data, cmdq->position, size, 0);
54 nvkm_falcon_pio_wr(falcon, data, 0, 0, DMEM, cmdq->position, size, 0, false);
55 cmdq->position += ALIGN(size, QUEUE_ALIGNMENT);
56}
57
58static void
59nvkm_falcon_cmdq_rewind(struct nvkm_falcon_cmdq *cmdq)
60{
61 struct nvfw_falcon_cmd cmd;
62

--- 152 unchanged lines hidden --- 		55 cmdq->position += ALIGN(size, QUEUE_ALIGNMENT);
56}
57
58static void
59nvkm_falcon_cmdq_rewind(struct nvkm_falcon_cmdq *cmdq)
60{
61 struct nvfw_falcon_cmd cmd;
62

--- 152 unchanged lines hidden ---