| hw.c (85a3685852d9ac7d92be9d824533c915a4597fa4) | hw.c (cb8bb9cedb6015eafd56ef9e9c5b2c216e8e7960) |
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| 1/* 2 * Copyright 2006 Dave Airlie 3 * Copyright 2007 Maarten Maathuis 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation --- 647 unchanged lines hidden (view full) --- 656} 657 658static void 659nv_load_state_ext(struct drm_device *dev, int head, 660 struct nv04_mode_state *state) 661{ 662 struct nouveau_drm *drm = nouveau_drm(dev); 663 struct nvif_device *device = &drm->device; | 1/* 2 * Copyright 2006 Dave Airlie 3 * Copyright 2007 Maarten Maathuis 4 * Copyright 2007-2009 Stuart Bennett 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation --- 647 unchanged lines hidden (view full) --- 656} 657 658static void 659nv_load_state_ext(struct drm_device *dev, int head, 660 struct nv04_mode_state *state) 661{ 662 struct nouveau_drm *drm = nouveau_drm(dev); 663 struct nvif_device *device = &drm->device; |
| 664 struct nvkm_timer *ptimer = nvxx_timer(device); | 664 struct nvkm_timer *tmr = nvxx_timer(device); |
| 665 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 666 uint32_t reg900; 667 int i; 668 669 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 670 if (nv_two_heads(dev)) 671 /* setting ENGINE_CTRL (EC) *must* come before 672 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in --- 63 unchanged lines hidden (view full) --- 736 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); 737 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); 738 } 739 /* NV11 and NV20 stop at 0x52. */ 740 if (nv_gf4_disp_arch(dev)) { 741 if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) { 742 /* Not waiting for vertical retrace before modifying 743 CRE_53/CRE_54 causes lockups. */ | 665 struct nv04_crtc_reg *regp = &state->crtc_reg[head]; 666 uint32_t reg900; 667 int i; 668 669 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) { 670 if (nv_two_heads(dev)) 671 /* setting ENGINE_CTRL (EC) *must* come before 672 * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in --- 63 unchanged lines hidden (view full) --- 736 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B); 737 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY); 738 } 739 /* NV11 and NV20 stop at 0x52. */ 740 if (nv_gf4_disp_arch(dev)) { 741 if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) { 742 /* Not waiting for vertical retrace before modifying 743 CRE_53/CRE_54 causes lockups. */ |
| 744 nvkm_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8); 745 nvkm_timer_wait_eq(ptimer, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0); | 744 nvkm_timer_wait_eq(tmr, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x8); 745 nvkm_timer_wait_eq(tmr, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0); |
| 746 } 747 748 wr_cio_state(dev, head, regp, NV_CIO_CRE_42); 749 wr_cio_state(dev, head, regp, NV_CIO_CRE_53); 750 wr_cio_state(dev, head, regp, NV_CIO_CRE_54); 751 752 for (i = 0; i < 0x10; i++) 753 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); --- 72 unchanged lines hidden --- | 746 } 747 748 wr_cio_state(dev, head, regp, NV_CIO_CRE_42); 749 wr_cio_state(dev, head, regp, NV_CIO_CRE_53); 750 wr_cio_state(dev, head, regp, NV_CIO_CRE_54); 751 752 for (i = 0; i < 0x10; i++) 753 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]); --- 72 unchanged lines hidden --- |