| ingenic-drm.h (640eee067d9aae0bb98d8706001976ff1affaf00) | ingenic-drm.h (bb85760572ca24a76c3de644ce45cfb69f5a731a) |
|---|---|
| 1/* SPDX-License-Identifier: GPL-2.0 */ 2// 3// Ingenic JZ47xx KMS driver - Register definitions and private API 4// 5// Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net> 6 7#ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H 8#define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H --- 110 unchanged lines hidden (view full) --- 119#define JZ_LCD_CTRL_DISABLE BIT(4) 120#define JZ_LCD_CTRL_ENABLE BIT(3) 121#define JZ_LCD_CTRL_BPP_1 0x0 122#define JZ_LCD_CTRL_BPP_2 0x1 123#define JZ_LCD_CTRL_BPP_4 0x2 124#define JZ_LCD_CTRL_BPP_8 0x3 125#define JZ_LCD_CTRL_BPP_15_16 0x4 126#define JZ_LCD_CTRL_BPP_18_24 0x5 | 1/* SPDX-License-Identifier: GPL-2.0 */ 2// 3// Ingenic JZ47xx KMS driver - Register definitions and private API 4// 5// Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net> 6 7#ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H 8#define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H --- 110 unchanged lines hidden (view full) --- 119#define JZ_LCD_CTRL_DISABLE BIT(4) 120#define JZ_LCD_CTRL_ENABLE BIT(3) 121#define JZ_LCD_CTRL_BPP_1 0x0 122#define JZ_LCD_CTRL_BPP_2 0x1 123#define JZ_LCD_CTRL_BPP_4 0x2 124#define JZ_LCD_CTRL_BPP_8 0x3 125#define JZ_LCD_CTRL_BPP_15_16 0x4 126#define JZ_LCD_CTRL_BPP_18_24 0x5 |
| 127#define JZ_LCD_CTRL_BPP_30 0x7 |
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| 127#define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7) 128 129#define JZ_LCD_CMD_SOF_IRQ BIT(31) 130#define JZ_LCD_CMD_EOF_IRQ BIT(30) 131#define JZ_LCD_CMD_ENABLE_PAL BIT(28) 132 133#define JZ_LCD_SYNC_MASK 0x3ff 134 --- 28 unchanged lines hidden (view full) --- 163struct drm_plane; 164struct drm_plane_state; 165struct platform_driver; 166 167void ingenic_drm_plane_config(struct device *dev, 168 struct drm_plane *plane, u32 fourcc); 169void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane); 170 | 128#define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7) 129 130#define JZ_LCD_CMD_SOF_IRQ BIT(31) 131#define JZ_LCD_CMD_EOF_IRQ BIT(30) 132#define JZ_LCD_CMD_ENABLE_PAL BIT(28) 133 134#define JZ_LCD_SYNC_MASK 0x3ff 135 --- 28 unchanged lines hidden (view full) --- 164struct drm_plane; 165struct drm_plane_state; 166struct platform_driver; 167 168void ingenic_drm_plane_config(struct device *dev, 169 struct drm_plane *plane, u32 fourcc); 170void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane); 171 |
| 172void ingenic_drm_sync_data(struct device *dev, 173 struct drm_plane_state *old_state, 174 struct drm_plane_state *state); 175 |
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| 171extern struct platform_driver *ingenic_ipu_driver_ptr; 172 173#endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */ | 176extern struct platform_driver *ingenic_ipu_driver_ptr; 177 178#endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */ |