| ingenic-drm.h (5d8dfaa71d87f742c53309b95cb6a8b274119027) | ingenic-drm.h (b807fd2c43fe008eb6f4083e196ea38dadad9680) |
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| 1/* SPDX-License-Identifier: GPL-2.0 */ 2// 3// Ingenic JZ47xx KMS driver - Register definitions and private API 4// 5// Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net> 6 7#ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H 8#define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H --- 30 unchanged lines hidden (view full) --- 39#define JZ_REG_LCD_KEY0 0x110 40#define JZ_REG_LCD_KEY1 0x114 41#define JZ_REG_LCD_ALPHA 0x118 42#define JZ_REG_LCD_IPUR 0x11c 43#define JZ_REG_LCD_XYP0 0x120 44#define JZ_REG_LCD_XYP1 0x124 45#define JZ_REG_LCD_SIZE0 0x128 46#define JZ_REG_LCD_SIZE1 0x12c | 1/* SPDX-License-Identifier: GPL-2.0 */ 2// 3// Ingenic JZ47xx KMS driver - Register definitions and private API 4// 5// Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net> 6 7#ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H 8#define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H --- 30 unchanged lines hidden (view full) --- 39#define JZ_REG_LCD_KEY0 0x110 40#define JZ_REG_LCD_KEY1 0x114 41#define JZ_REG_LCD_ALPHA 0x118 42#define JZ_REG_LCD_IPUR 0x11c 43#define JZ_REG_LCD_XYP0 0x120 44#define JZ_REG_LCD_XYP1 0x124 45#define JZ_REG_LCD_SIZE0 0x128 46#define JZ_REG_LCD_SIZE1 0x12c |
| 47#define JZ_REG_LCD_PCFG 0x2c0 |
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| 47 48#define JZ_LCD_CFG_SLCD BIT(31) | 48 49#define JZ_LCD_CFG_SLCD BIT(31) |
| 50#define JZ_LCD_CFG_DESCRIPTOR_8 BIT(28) 51#define JZ_LCD_CFG_RECOVER_FIFO_UNDERRUN BIT(25) |
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| 49#define JZ_LCD_CFG_PS_DISABLE BIT(23) 50#define JZ_LCD_CFG_CLS_DISABLE BIT(22) 51#define JZ_LCD_CFG_SPL_DISABLE BIT(21) 52#define JZ_LCD_CFG_REV_DISABLE BIT(20) 53#define JZ_LCD_CFG_HSYNCM BIT(19) 54#define JZ_LCD_CFG_PCLKM BIT(18) 55#define JZ_LCD_CFG_INV BIT(17) 56#define JZ_LCD_CFG_SYNC_DIR BIT(16) 57#define JZ_LCD_CFG_PS_POLARITY BIT(15) 58#define JZ_LCD_CFG_CLS_POLARITY BIT(14) 59#define JZ_LCD_CFG_SPL_POLARITY BIT(13) 60#define JZ_LCD_CFG_REV_POLARITY BIT(12) 61#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11) 62#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10) 63#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) 64#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8) 65#define JZ_LCD_CFG_18_BIT BIT(7) | 52#define JZ_LCD_CFG_PS_DISABLE BIT(23) 53#define JZ_LCD_CFG_CLS_DISABLE BIT(22) 54#define JZ_LCD_CFG_SPL_DISABLE BIT(21) 55#define JZ_LCD_CFG_REV_DISABLE BIT(20) 56#define JZ_LCD_CFG_HSYNCM BIT(19) 57#define JZ_LCD_CFG_PCLKM BIT(18) 58#define JZ_LCD_CFG_INV BIT(17) 59#define JZ_LCD_CFG_SYNC_DIR BIT(16) 60#define JZ_LCD_CFG_PS_POLARITY BIT(15) 61#define JZ_LCD_CFG_CLS_POLARITY BIT(14) 62#define JZ_LCD_CFG_SPL_POLARITY BIT(13) 63#define JZ_LCD_CFG_REV_POLARITY BIT(12) 64#define JZ_LCD_CFG_HSYNC_ACTIVE_LOW BIT(11) 65#define JZ_LCD_CFG_PCLK_FALLING_EDGE BIT(10) 66#define JZ_LCD_CFG_DE_ACTIVE_LOW BIT(9) 67#define JZ_LCD_CFG_VSYNC_ACTIVE_LOW BIT(8) 68#define JZ_LCD_CFG_18_BIT BIT(7) |
| 69#define JZ_LCD_CFG_24_BIT BIT(6) |
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| 66#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) 67 68#define JZ_LCD_CFG_MODE_GENERIC_16BIT 0 69#define JZ_LCD_CFG_MODE_GENERIC_18BIT BIT(7) 70#define JZ_LCD_CFG_MODE_GENERIC_24BIT BIT(6) 71 72#define JZ_LCD_CFG_MODE_SPECIAL_TFT_1 1 73#define JZ_LCD_CFG_MODE_SPECIAL_TFT_2 2 --- 53 unchanged lines hidden (view full) --- 127#define JZ_LCD_CTRL_BPP_18_24 0x5 128#define JZ_LCD_CTRL_BPP_24_COMP 0x6 129#define JZ_LCD_CTRL_BPP_30 0x7 130#define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7) 131 132#define JZ_LCD_CMD_SOF_IRQ BIT(31) 133#define JZ_LCD_CMD_EOF_IRQ BIT(30) 134#define JZ_LCD_CMD_ENABLE_PAL BIT(28) | 70#define JZ_LCD_CFG_PDW (BIT(5) | BIT(4)) 71 72#define JZ_LCD_CFG_MODE_GENERIC_16BIT 0 73#define JZ_LCD_CFG_MODE_GENERIC_18BIT BIT(7) 74#define JZ_LCD_CFG_MODE_GENERIC_24BIT BIT(6) 75 76#define JZ_LCD_CFG_MODE_SPECIAL_TFT_1 1 77#define JZ_LCD_CFG_MODE_SPECIAL_TFT_2 2 --- 53 unchanged lines hidden (view full) --- 131#define JZ_LCD_CTRL_BPP_18_24 0x5 132#define JZ_LCD_CTRL_BPP_24_COMP 0x6 133#define JZ_LCD_CTRL_BPP_30 0x7 134#define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7) 135 136#define JZ_LCD_CMD_SOF_IRQ BIT(31) 137#define JZ_LCD_CMD_EOF_IRQ BIT(30) 138#define JZ_LCD_CMD_ENABLE_PAL BIT(28) |
| 139#define JZ_LCD_CMD_FRM_ENABLE BIT(26) |
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| 135 136#define JZ_LCD_SYNC_MASK 0x3ff 137 138#define JZ_LCD_STATE_EOF_IRQ BIT(5) 139#define JZ_LCD_STATE_SOF_IRQ BIT(4) 140#define JZ_LCD_STATE_DISABLED BIT(0) 141 142#define JZ_LCD_RGBC_ODD_RGB (0x0 << 4) --- 5 unchanged lines hidden (view full) --- 148#define JZ_LCD_RGBC_EVEN_RGB (0x0 << 0) 149#define JZ_LCD_RGBC_EVEN_RBG (0x1 << 0) 150#define JZ_LCD_RGBC_EVEN_GRB (0x2 << 0) 151#define JZ_LCD_RGBC_EVEN_GBR (0x3 << 0) 152#define JZ_LCD_RGBC_EVEN_BRG (0x4 << 0) 153#define JZ_LCD_RGBC_EVEN_BGR (0x5 << 0) 154 155#define JZ_LCD_OSDC_OSDEN BIT(0) | 140 141#define JZ_LCD_SYNC_MASK 0x3ff 142 143#define JZ_LCD_STATE_EOF_IRQ BIT(5) 144#define JZ_LCD_STATE_SOF_IRQ BIT(4) 145#define JZ_LCD_STATE_DISABLED BIT(0) 146 147#define JZ_LCD_RGBC_ODD_RGB (0x0 << 4) --- 5 unchanged lines hidden (view full) --- 153#define JZ_LCD_RGBC_EVEN_RGB (0x0 << 0) 154#define JZ_LCD_RGBC_EVEN_RBG (0x1 << 0) 155#define JZ_LCD_RGBC_EVEN_GRB (0x2 << 0) 156#define JZ_LCD_RGBC_EVEN_GBR (0x3 << 0) 157#define JZ_LCD_RGBC_EVEN_BRG (0x4 << 0) 158#define JZ_LCD_RGBC_EVEN_BGR (0x5 << 0) 159 160#define JZ_LCD_OSDC_OSDEN BIT(0) |
| 161#define JZ_LCD_OSDC_ALPHAEN BIT(2) |
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| 156#define JZ_LCD_OSDC_F0EN BIT(3) 157#define JZ_LCD_OSDC_F1EN BIT(4) 158 159#define JZ_LCD_OSDCTRL_IPU BIT(15) 160#define JZ_LCD_OSDCTRL_RGB555 BIT(4) 161#define JZ_LCD_OSDCTRL_CHANGE BIT(3) 162#define JZ_LCD_OSDCTRL_BPP_15_16 0x4 163#define JZ_LCD_OSDCTRL_BPP_18_24 0x5 --- 7 unchanged lines hidden (view full) --- 171#define JZ_LCD_IPUR_IPUR_LSB 0 172 173#define JZ_LCD_XYP01_XPOS_LSB 0 174#define JZ_LCD_XYP01_YPOS_LSB 16 175 176#define JZ_LCD_SIZE01_WIDTH_LSB 0 177#define JZ_LCD_SIZE01_HEIGHT_LSB 16 178 | 162#define JZ_LCD_OSDC_F0EN BIT(3) 163#define JZ_LCD_OSDC_F1EN BIT(4) 164 165#define JZ_LCD_OSDCTRL_IPU BIT(15) 166#define JZ_LCD_OSDCTRL_RGB555 BIT(4) 167#define JZ_LCD_OSDCTRL_CHANGE BIT(3) 168#define JZ_LCD_OSDCTRL_BPP_15_16 0x4 169#define JZ_LCD_OSDCTRL_BPP_18_24 0x5 --- 7 unchanged lines hidden (view full) --- 177#define JZ_LCD_IPUR_IPUR_LSB 0 178 179#define JZ_LCD_XYP01_XPOS_LSB 0 180#define JZ_LCD_XYP01_YPOS_LSB 16 181 182#define JZ_LCD_SIZE01_WIDTH_LSB 0 183#define JZ_LCD_SIZE01_HEIGHT_LSB 16 184 |
| 185#define JZ_LCD_DESSIZE_ALPHA_OFFSET 24 186#define JZ_LCD_DESSIZE_HEIGHT_MASK GENMASK(23, 12) 187#define JZ_LCD_DESSIZE_WIDTH_MASK GENMASK(11, 0) 188 189#define JZ_LCD_CPOS_BPP_15_16 (4 << 27) 190#define JZ_LCD_CPOS_BPP_18_24 (5 << 27) 191#define JZ_LCD_CPOS_BPP_30 (7 << 27) 192#define JZ_LCD_CPOS_RGB555 BIT(30) 193#define JZ_LCD_CPOS_PREMULTIPLY_LCD BIT(26) 194#define JZ_LCD_CPOS_COEFFICIENT_OFFSET 24 195#define JZ_LCD_CPOS_COEFFICIENT_0 0 196#define JZ_LCD_CPOS_COEFFICIENT_1 1 197#define JZ_LCD_CPOS_COEFFICIENT_ALPHA1 2 198#define JZ_LCD_CPOS_COEFFICIENT_1_ALPHA1 3 199 200#define JZ_LCD_RGBC_RGB_PADDING BIT(15) 201#define JZ_LCD_RGBC_RGB_PADDING_FIRST BIT(14) 202#define JZ_LCD_RGBC_422 BIT(8) 203#define JZ_LCD_RGBC_RGB_FORMAT_ENABLE BIT(7) 204 205#define JZ_LCD_PCFG_PRI_MODE BIT(31) 206#define JZ_LCD_PCFG_HP_BST_4 (0 << 28) 207#define JZ_LCD_PCFG_HP_BST_8 (1 << 28) 208#define JZ_LCD_PCFG_HP_BST_16 (2 << 28) 209#define JZ_LCD_PCFG_HP_BST_32 (3 << 28) 210#define JZ_LCD_PCFG_HP_BST_64 (4 << 28) 211#define JZ_LCD_PCFG_HP_BST_16_CONT (5 << 28) 212#define JZ_LCD_PCFG_HP_BST_DISABLE (7 << 28) 213#define JZ_LCD_PCFG_THRESHOLD2_OFFSET 18 214#define JZ_LCD_PCFG_THRESHOLD1_OFFSET 9 215#define JZ_LCD_PCFG_THRESHOLD0_OFFSET 0 216 |
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| 179struct device; 180struct drm_plane; 181struct drm_plane_state; 182struct platform_driver; 183 184void ingenic_drm_plane_config(struct device *dev, 185 struct drm_plane *plane, u32 fourcc); 186void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane); 187bool ingenic_drm_map_noncoherent(const struct device *dev); 188 189extern struct platform_driver *ingenic_ipu_driver_ptr; 190 191#endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */ | 217struct device; 218struct drm_plane; 219struct drm_plane_state; 220struct platform_driver; 221 222void ingenic_drm_plane_config(struct device *dev, 223 struct drm_plane *plane, u32 fourcc); 224void ingenic_drm_plane_disable(struct device *dev, struct drm_plane *plane); 225bool ingenic_drm_map_noncoherent(const struct device *dev); 226 227extern struct platform_driver *ingenic_ipu_driver_ptr; 228 229#endif /* DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H */ |