| ingenic-drm.h (05909cd9a0c8811731b38697af13075e8954314f) | ingenic-drm.h (ca459a7407a2f5c3bad4eb5656ed654b9d3d3579) |
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| 1/* SPDX-License-Identifier: GPL-2.0 */ 2// 3// Ingenic JZ47xx KMS driver - Register definitions and private API 4// 5// Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net> 6 7#ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H 8#define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H --- 17 unchanged lines hidden (view full) --- 26#define JZ_REG_LCD_DA0 0x40 27#define JZ_REG_LCD_SA0 0x44 28#define JZ_REG_LCD_FID0 0x48 29#define JZ_REG_LCD_CMD0 0x4C 30#define JZ_REG_LCD_DA1 0x50 31#define JZ_REG_LCD_SA1 0x54 32#define JZ_REG_LCD_FID1 0x58 33#define JZ_REG_LCD_CMD1 0x5C | 1/* SPDX-License-Identifier: GPL-2.0 */ 2// 3// Ingenic JZ47xx KMS driver - Register definitions and private API 4// 5// Copyright (C) 2020, Paul Cercueil <paul@crapouillou.net> 6 7#ifndef DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H 8#define DRIVERS_GPU_DRM_INGENIC_INGENIC_DRM_H --- 17 unchanged lines hidden (view full) --- 26#define JZ_REG_LCD_DA0 0x40 27#define JZ_REG_LCD_SA0 0x44 28#define JZ_REG_LCD_FID0 0x48 29#define JZ_REG_LCD_CMD0 0x4C 30#define JZ_REG_LCD_DA1 0x50 31#define JZ_REG_LCD_SA1 0x54 32#define JZ_REG_LCD_FID1 0x58 33#define JZ_REG_LCD_CMD1 0x5C |
| 34#define JZ_REG_LCD_RGBC 0x90 |
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| 34#define JZ_REG_LCD_OSDC 0x100 35#define JZ_REG_LCD_OSDCTRL 0x104 36#define JZ_REG_LCD_OSDS 0x108 37#define JZ_REG_LCD_BGC 0x10c 38#define JZ_REG_LCD_KEY0 0x110 39#define JZ_REG_LCD_KEY1 0x114 40#define JZ_REG_LCD_ALPHA 0x118 41#define JZ_REG_LCD_IPUR 0x11c --- 77 unchanged lines hidden (view full) --- 119#define JZ_LCD_CTRL_DISABLE BIT(4) 120#define JZ_LCD_CTRL_ENABLE BIT(3) 121#define JZ_LCD_CTRL_BPP_1 0x0 122#define JZ_LCD_CTRL_BPP_2 0x1 123#define JZ_LCD_CTRL_BPP_4 0x2 124#define JZ_LCD_CTRL_BPP_8 0x3 125#define JZ_LCD_CTRL_BPP_15_16 0x4 126#define JZ_LCD_CTRL_BPP_18_24 0x5 | 35#define JZ_REG_LCD_OSDC 0x100 36#define JZ_REG_LCD_OSDCTRL 0x104 37#define JZ_REG_LCD_OSDS 0x108 38#define JZ_REG_LCD_BGC 0x10c 39#define JZ_REG_LCD_KEY0 0x110 40#define JZ_REG_LCD_KEY1 0x114 41#define JZ_REG_LCD_ALPHA 0x118 42#define JZ_REG_LCD_IPUR 0x11c --- 77 unchanged lines hidden (view full) --- 120#define JZ_LCD_CTRL_DISABLE BIT(4) 121#define JZ_LCD_CTRL_ENABLE BIT(3) 122#define JZ_LCD_CTRL_BPP_1 0x0 123#define JZ_LCD_CTRL_BPP_2 0x1 124#define JZ_LCD_CTRL_BPP_4 0x2 125#define JZ_LCD_CTRL_BPP_8 0x3 126#define JZ_LCD_CTRL_BPP_15_16 0x4 127#define JZ_LCD_CTRL_BPP_18_24 0x5 |
| 128#define JZ_LCD_CTRL_BPP_24_COMP 0x6 129#define JZ_LCD_CTRL_BPP_30 0x7 |
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| 127#define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7) 128 129#define JZ_LCD_CMD_SOF_IRQ BIT(31) 130#define JZ_LCD_CMD_EOF_IRQ BIT(30) 131#define JZ_LCD_CMD_ENABLE_PAL BIT(28) 132 133#define JZ_LCD_SYNC_MASK 0x3ff 134 135#define JZ_LCD_STATE_EOF_IRQ BIT(5) 136#define JZ_LCD_STATE_SOF_IRQ BIT(4) 137#define JZ_LCD_STATE_DISABLED BIT(0) 138 | 130#define JZ_LCD_CTRL_BPP_MASK (JZ_LCD_CTRL_RGB555 | 0x7) 131 132#define JZ_LCD_CMD_SOF_IRQ BIT(31) 133#define JZ_LCD_CMD_EOF_IRQ BIT(30) 134#define JZ_LCD_CMD_ENABLE_PAL BIT(28) 135 136#define JZ_LCD_SYNC_MASK 0x3ff 137 138#define JZ_LCD_STATE_EOF_IRQ BIT(5) 139#define JZ_LCD_STATE_SOF_IRQ BIT(4) 140#define JZ_LCD_STATE_DISABLED BIT(0) 141 |
| 142#define JZ_LCD_RGBC_ODD_RGB (0x0 << 4) 143#define JZ_LCD_RGBC_ODD_RBG (0x1 << 4) 144#define JZ_LCD_RGBC_ODD_GRB (0x2 << 4) 145#define JZ_LCD_RGBC_ODD_GBR (0x3 << 4) 146#define JZ_LCD_RGBC_ODD_BRG (0x4 << 4) 147#define JZ_LCD_RGBC_ODD_BGR (0x5 << 4) 148#define JZ_LCD_RGBC_EVEN_RGB (0x0 << 0) 149#define JZ_LCD_RGBC_EVEN_RBG (0x1 << 0) 150#define JZ_LCD_RGBC_EVEN_GRB (0x2 << 0) 151#define JZ_LCD_RGBC_EVEN_GBR (0x3 << 0) 152#define JZ_LCD_RGBC_EVEN_BRG (0x4 << 0) 153#define JZ_LCD_RGBC_EVEN_BGR (0x5 << 0) 154 |
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| 139#define JZ_LCD_OSDC_OSDEN BIT(0) 140#define JZ_LCD_OSDC_F0EN BIT(3) 141#define JZ_LCD_OSDC_F1EN BIT(4) 142 143#define JZ_LCD_OSDCTRL_IPU BIT(15) 144#define JZ_LCD_OSDCTRL_RGB555 BIT(4) 145#define JZ_LCD_OSDCTRL_CHANGE BIT(3) 146#define JZ_LCD_OSDCTRL_BPP_15_16 0x4 147#define JZ_LCD_OSDCTRL_BPP_18_24 0x5 | 155#define JZ_LCD_OSDC_OSDEN BIT(0) 156#define JZ_LCD_OSDC_F0EN BIT(3) 157#define JZ_LCD_OSDC_F1EN BIT(4) 158 159#define JZ_LCD_OSDCTRL_IPU BIT(15) 160#define JZ_LCD_OSDCTRL_RGB555 BIT(4) 161#define JZ_LCD_OSDCTRL_CHANGE BIT(3) 162#define JZ_LCD_OSDCTRL_BPP_15_16 0x4 163#define JZ_LCD_OSDCTRL_BPP_18_24 0x5 |
| 164#define JZ_LCD_OSDCTRL_BPP_24_COMP 0x6 |
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| 148#define JZ_LCD_OSDCTRL_BPP_30 0x7 149#define JZ_LCD_OSDCTRL_BPP_MASK (JZ_LCD_OSDCTRL_RGB555 | 0x7) 150 151#define JZ_LCD_OSDS_READY BIT(0) 152 153#define JZ_LCD_IPUR_IPUREN BIT(31) 154#define JZ_LCD_IPUR_IPUR_LSB 0 155 --- 18 unchanged lines hidden --- | 165#define JZ_LCD_OSDCTRL_BPP_30 0x7 166#define JZ_LCD_OSDCTRL_BPP_MASK (JZ_LCD_OSDCTRL_RGB555 | 0x7) 167 168#define JZ_LCD_OSDS_READY BIT(0) 169 170#define JZ_LCD_IPUR_IPUREN BIT(31) 171#define JZ_LCD_IPUR_IPUR_LSB 0 172 --- 18 unchanged lines hidden --- |