display.h (6a4500c7b83f9e4470dd20cf89f691abd132d090) display.h (b01739fb865a268aec617f6bb5d2ef498da72697)
1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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31 * Zhi Wang <zhi.a.wang@intel.com>
32 *
33 */
34
35#ifndef _GVT_DISPLAY_H_
36#define _GVT_DISPLAY_H_
37
38#include <linux/types.h>
1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 22 unchanged lines hidden (view full) ---

31 * Zhi Wang <zhi.a.wang@intel.com>
32 *
33 */
34
35#ifndef _GVT_DISPLAY_H_
36#define _GVT_DISPLAY_H_
37
38#include <linux/types.h>
39#include <linux/hrtimer.h>
39
40struct intel_gvt;
41struct intel_vgpu;
42
43#define SBI_REG_MAX 20
44#define DPCD_SIZE 0x700
45
46#define intel_vgpu_port(vgpu, port) \

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164 /* per display DPCD information */
165 struct intel_vgpu_dpcd_data *dpcd;
166 int type;
167 enum intel_vgpu_edid id;
168 /* x1000 to get accurate 59.94, 24.976, 29.94, etc. in timing std. */
169 u32 vrefresh_k;
170};
171
40
41struct intel_gvt;
42struct intel_vgpu;
43
44#define SBI_REG_MAX 20
45#define DPCD_SIZE 0x700
46
47#define intel_vgpu_port(vgpu, port) \

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165 /* per display DPCD information */
166 struct intel_vgpu_dpcd_data *dpcd;
167 int type;
168 enum intel_vgpu_edid id;
169 /* x1000 to get accurate 59.94, 24.976, 29.94, etc. in timing std. */
170 u32 vrefresh_k;
171};
172
173struct intel_vgpu_vblank_timer {
174 struct hrtimer timer;
175 u32 vrefresh_k;
176 u64 period;
177};
178
172static inline char *vgpu_edid_str(enum intel_vgpu_edid id)
173{
174 switch (id) {
175 case GVT_EDID_1024_768:
176 return "1024x768";
177 case GVT_EDID_1920_1200:
178 return "1920x1200";
179 default:

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200 return 768;
201 case GVT_EDID_1920_1200:
202 return 1200;
203 default:
204 return 0;
205 }
206}
207
179static inline char *vgpu_edid_str(enum intel_vgpu_edid id)
180{
181 switch (id) {
182 case GVT_EDID_1024_768:
183 return "1024x768";
184 case GVT_EDID_1920_1200:
185 return "1920x1200";
186 default:

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207 return 768;
208 case GVT_EDID_1920_1200:
209 return 1200;
210 default:
211 return 0;
212 }
213}
214
208void intel_gvt_emulate_vblank(struct intel_gvt *gvt);
209void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt);
215void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu);
216void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon);
210
211int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution);
212void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
213void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
214
215int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
216
217#endif
217
218int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution);
219void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
220void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
221
222int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
223
224#endif