vid.h (06be5eefe1192eb8ce8d07497f67595b6bfe9741) vid.h (ff758a12b45b0513dbe9905deba2a29b20412138)
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

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61#define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898)
62#define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898)
63#define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898)
64#define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898)
65#define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898)
66
67#define AMDGPU_NUM_OF_VMIDS 8
68
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the

--- 52 unchanged lines hidden (view full) ---

61#define HPD1_REGISTER_OFFSET (0x18a0 - 0x1898)
62#define HPD2_REGISTER_OFFSET (0x18a8 - 0x1898)
63#define HPD3_REGISTER_OFFSET (0x18b0 - 0x1898)
64#define HPD4_REGISTER_OFFSET (0x18b8 - 0x1898)
65#define HPD5_REGISTER_OFFSET (0x18c0 - 0x1898)
66
67#define AMDGPU_NUM_OF_VMIDS 8
68
69#define PIPEID(x) ((x) << 0)
70#define MEID(x) ((x) << 2)
71#define VMID(x) ((x) << 4)
72#define QUEUEID(x) ((x) << 8)
73
69#define RB_BITMAP_WIDTH_PER_SH 2
70
71#define MC_SEQ_MISC0__MT__MASK 0xf0000000
72#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
73#define MC_SEQ_MISC0__MT__DDR2 0x20000000
74#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
75#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
76#define MC_SEQ_MISC0__MT__GDDR5 0x50000000

--- 292 unchanged lines hidden --- 		74#define RB_BITMAP_WIDTH_PER_SH 2
75
76#define MC_SEQ_MISC0__MT__MASK 0xf0000000
77#define MC_SEQ_MISC0__MT__GDDR1 0x10000000
78#define MC_SEQ_MISC0__MT__DDR2 0x20000000
79#define MC_SEQ_MISC0__MT__GDDR3 0x30000000
80#define MC_SEQ_MISC0__MT__GDDR4 0x40000000
81#define MC_SEQ_MISC0__MT__GDDR5 0x50000000

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