amdgpu.h (585a78c1f77be305b1f6adad392f16047fb66ffd) amdgpu.h (c103a23f2f297c6ab2e5e74e39b655439f3524a6)
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 38 unchanged lines hidden (view full) ---

47#include <linux/list.h>
48#include <linux/kref.h>
49#include <linux/rbtree.h>
50#include <linux/hashtable.h>
51#include <linux/dma-fence.h>
52#include <linux/pci.h>
53#include <linux/aer.h>
54
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation

--- 38 unchanged lines hidden (view full) ---

47#include <linux/list.h>
48#include <linux/kref.h>
49#include <linux/rbtree.h>
50#include <linux/hashtable.h>
51#include <linux/dma-fence.h>
52#include <linux/pci.h>
53#include <linux/aer.h>
54
55#include <drm/ttm/ttm_bo_api.h>
56#include <drm/ttm/ttm_bo_driver.h>
55#include <drm/ttm/ttm_bo.h>
57#include <drm/ttm/ttm_placement.h>
58#include <drm/ttm/ttm_execbuf_util.h>
59
60#include <drm/amdgpu_drm.h>
61#include <drm/drm_gem.h>
62#include <drm/drm_ioctl.h>
63
64#include <kgd_kfd_interface.h>

--- 80 unchanged lines hidden (view full) ---

145};
146
147#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
148
149/*
150 * Modules parameters.
151 */
152extern int amdgpu_modeset;
56#include <drm/ttm/ttm_placement.h>
57#include <drm/ttm/ttm_execbuf_util.h>
58
59#include <drm/amdgpu_drm.h>
60#include <drm/drm_gem.h>
61#include <drm/drm_ioctl.h>
62
63#include <kgd_kfd_interface.h>

--- 80 unchanged lines hidden (view full) ---

144};
145
146#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH 256
147
148/*
149 * Modules parameters.
150 */
151extern int amdgpu_modeset;
153extern int amdgpu_vram_limit;
152extern unsigned int amdgpu_vram_limit;
154extern int amdgpu_vis_vram_limit;
155extern int amdgpu_gart_size;
156extern int amdgpu_gtt_size;
157extern int amdgpu_moverate;
158extern int amdgpu_audio;
159extern int amdgpu_disp_priority;
160extern int amdgpu_hw_i2c;
161extern int amdgpu_pcie_gen2;

--- 76 unchanged lines hidden (view full) ---

238#endif
239#ifdef CONFIG_DRM_AMDGPU_CIK
240extern int amdgpu_cik_support;
241#endif
242extern int amdgpu_num_kcq;
243
244#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
245extern int amdgpu_vcnfw_log;
153extern int amdgpu_vis_vram_limit;
154extern int amdgpu_gart_size;
155extern int amdgpu_gtt_size;
156extern int amdgpu_moverate;
157extern int amdgpu_audio;
158extern int amdgpu_disp_priority;
159extern int amdgpu_hw_i2c;
160extern int amdgpu_pcie_gen2;

--- 76 unchanged lines hidden (view full) ---

237#endif
238#ifdef CONFIG_DRM_AMDGPU_CIK
239extern int amdgpu_cik_support;
240#endif
241extern int amdgpu_num_kcq;
242
243#define AMDGPU_VCNFW_LOG_SIZE (32 * 1024)
244extern int amdgpu_vcnfw_log;
246extern int amdgpu_sg_display;
247
248#define AMDGPU_VM_MAX_NUM_CTX 4096
249#define AMDGPU_SG_THRESHOLD (256*1024*1024)
250#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
251#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
252#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
253#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
254#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32

--- 165 unchanged lines hidden (view full) ---

420 *
421 * Alignment can't be bigger than page size.
422 *
423 * Hole are not considered for allocation to keep things simple.
424 * Assumption is that there won't be hole (all object on same
425 * alignment).
426 */
427
245
246#define AMDGPU_VM_MAX_NUM_CTX 4096
247#define AMDGPU_SG_THRESHOLD (256*1024*1024)
248#define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
249#define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
250#define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
251#define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
252#define AMDGPU_DEBUGFS_MAX_COMPONENTS 32

--- 165 unchanged lines hidden (view full) ---

418 *
419 * Alignment can't be bigger than page size.
420 *
421 * Hole are not considered for allocation to keep things simple.
422 * Assumption is that there won't be hole (all object on same
423 * alignment).
424 */
425
428#define AMDGPU_SA_NUM_FENCE_LISTS 32
429
430struct amdgpu_sa_manager {
426struct amdgpu_sa_manager {
431 wait_queue_head_t wq;
432 struct amdgpu_bo *bo;
433 struct list_head *hole;
434 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
435 struct list_head olist;
436 unsigned size;
437 uint64_t gpu_addr;
438 void *cpu_ptr;
439 uint32_t domain;
440 uint32_t align;
427 struct drm_suballoc_manager base;
428 struct amdgpu_bo *bo;
429 uint64_t gpu_addr;
430 void *cpu_ptr;
441};
442
431};
432
443/* sub-allocation buffer */
444struct amdgpu_sa_bo {
445 struct list_head olist;
446 struct list_head flist;
447 struct amdgpu_sa_manager *manager;
448 unsigned soffset;
449 unsigned eoffset;
450 struct dma_fence *fence;
451};
452
453int amdgpu_fence_slab_init(void);
454void amdgpu_fence_slab_fini(void);
455
456/*
457 * IRQS.
458 */
459
460struct amdgpu_flip_work {

--- 144 unchanged lines hidden (view full) ---

605int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
606int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
607 struct drm_file *filp);
608int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
609int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
610 struct drm_file *filp);
611
612/* VRAM scratch page for HDP bug, default vram page */
433int amdgpu_fence_slab_init(void);
434void amdgpu_fence_slab_fini(void);
435
436/*
437 * IRQS.
438 */
439
440struct amdgpu_flip_work {

--- 144 unchanged lines hidden (view full) ---

585int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
586int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
587 struct drm_file *filp);
588int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
589int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
590 struct drm_file *filp);
591
592/* VRAM scratch page for HDP bug, default vram page */
613struct amdgpu_vram_scratch {
593struct amdgpu_mem_scratch {
614 struct amdgpu_bo *robj;
615 volatile uint32_t *ptr;
616 u64 gpu_addr;
617};
618
619/*
620 * CGS
621 */

--- 130 unchanged lines hidden (view full) ---

752 struct amdgpu_mqd_prop *p);
753};
754
755#define AMDGPU_RESET_MAGIC_NUM 64
756#define AMDGPU_MAX_DF_PERFMONS 4
757#define AMDGPU_PRODUCT_NAME_LEN 64
758struct amdgpu_reset_domain;
759
594 struct amdgpu_bo *robj;
595 volatile uint32_t *ptr;
596 u64 gpu_addr;
597};
598
599/*
600 * CGS
601 */

--- 130 unchanged lines hidden (view full) ---

732 struct amdgpu_mqd_prop *p);
733};
734
735#define AMDGPU_RESET_MAGIC_NUM 64
736#define AMDGPU_MAX_DF_PERFMONS 4
737#define AMDGPU_PRODUCT_NAME_LEN 64
738struct amdgpu_reset_domain;
739
740/*
741 * Non-zero (true) if the GPU has VRAM. Zero (false) otherwise.
742 */
743#define AMDGPU_HAS_VRAM(_adev) ((_adev)->gmc.real_vram_size)
744
760struct amdgpu_device {
761 struct device *dev;
762 struct pci_dev *pdev;
763 struct drm_device ddev;
764
765#ifdef CONFIG_DRM_AMD_ACP
766 struct amdgpu_acp acp;
767#endif

--- 77 unchanged lines hidden (view full) ---

845 struct amdgpu_gart gart;
846 dma_addr_t dummy_page_addr;
847 struct amdgpu_vm_manager vm_manager;
848 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
849 unsigned num_vmhubs;
850
851 /* memory management */
852 struct amdgpu_mman mman;
745struct amdgpu_device {
746 struct device *dev;
747 struct pci_dev *pdev;
748 struct drm_device ddev;
749
750#ifdef CONFIG_DRM_AMD_ACP
751 struct amdgpu_acp acp;
752#endif

--- 77 unchanged lines hidden (view full) ---

830 struct amdgpu_gart gart;
831 dma_addr_t dummy_page_addr;
832 struct amdgpu_vm_manager vm_manager;
833 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
834 unsigned num_vmhubs;
835
836 /* memory management */
837 struct amdgpu_mman mman;
853 struct amdgpu_vram_scratch vram_scratch;
838 struct amdgpu_mem_scratch mem_scratch;
854 struct amdgpu_wb wb;
855 atomic64_t num_bytes_moved;
856 atomic64_t num_evictions;
857 atomic64_t num_vram_cpu_page_faults;
858 atomic_t gpu_reset_counter;
859 atomic_t vram_lost_counter;
860
861 /* data for buffer migration throttling */

--- 5 unchanged lines hidden (view full) ---

867 u32 log2_max_MBps;
868 } mm_stats;
869
870 /* display */
871 bool enable_virtual_display;
872 struct amdgpu_vkms_output *amdgpu_vkms_output;
873 struct amdgpu_mode_info mode_info;
874 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
839 struct amdgpu_wb wb;
840 atomic64_t num_bytes_moved;
841 atomic64_t num_evictions;
842 atomic64_t num_vram_cpu_page_faults;
843 atomic_t gpu_reset_counter;
844 atomic_t vram_lost_counter;
845
846 /* data for buffer migration throttling */

--- 5 unchanged lines hidden (view full) ---

852 u32 log2_max_MBps;
853 } mm_stats;
854
855 /* display */
856 bool enable_virtual_display;
857 struct amdgpu_vkms_output *amdgpu_vkms_output;
858 struct amdgpu_mode_info mode_info;
859 /* For pre-DCE11. DCE11 and later are in "struct amdgpu_device->dm" */
875 struct work_struct hotplug_work;
860 struct delayed_work hotplug_work;
876 struct amdgpu_irq_src crtc_irq;
877 struct amdgpu_irq_src vline0_irq;
878 struct amdgpu_irq_src vupdate_irq;
879 struct amdgpu_irq_src pageflip_irq;
880 struct amdgpu_irq_src hpd_irq;
881 struct amdgpu_irq_src dmub_trace_irq;
882 struct amdgpu_irq_src dmub_outbox_irq;
883

--- 573 unchanged lines hidden --- 		861 struct amdgpu_irq_src crtc_irq;
862 struct amdgpu_irq_src vline0_irq;
863 struct amdgpu_irq_src vupdate_irq;
864 struct amdgpu_irq_src pageflip_irq;
865 struct amdgpu_irq_src hpd_irq;
866 struct amdgpu_irq_src dmub_trace_irq;
867 struct amdgpu_irq_src dmub_outbox_irq;
868

--- 573 unchanged lines hidden ---