gpio-wcove.c (9095bf25ea08135a5b74875dd0e3eeaddc4218a0) gpio-wcove.c (881ebd229f4a5ea88f269c1225245e50db9ba303)
1/*
2 * Intel Whiskey Cove PMIC GPIO Driver
3 *
4 * This driver is written based on gpio-crystalcove.c
5 *
6 * Copyright (C) 2016 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or

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46 * Group 0: Bank 0 pins (Pin 0 - 6)
47 * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
48 * Each group has two registers (one bit per pin): status and mask.
49 */
50#define GROUP0_NR_IRQS 7
51#define GROUP1_NR_IRQS 6
52#define IRQ_MASK_BASE 0x4e19
53#define IRQ_STATUS_BASE 0x4e0b
1/*
2 * Intel Whiskey Cove PMIC GPIO Driver
3 *
4 * This driver is written based on gpio-crystalcove.c
5 *
6 * Copyright (C) 2016 Intel Corporation. All rights reserved.
7 *
8 * This program is free software; you can redistribute it and/or

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46 * Group 0: Bank 0 pins (Pin 0 - 6)
47 * Group 1: Bank 1 and Bank 2 pins (Pin 7 - 12)
48 * Each group has two registers (one bit per pin): status and mask.
49 */
50#define GROUP0_NR_IRQS 7
51#define GROUP1_NR_IRQS 6
52#define IRQ_MASK_BASE 0x4e19
53#define IRQ_STATUS_BASE 0x4e0b
54#define GPIO_IRQ0_MASK GENMASK(6, 0)
55#define GPIO_IRQ1_MASK GENMASK(5, 0)
54#define UPDATE_IRQ_TYPE BIT(0)
55#define UPDATE_IRQ_MASK BIT(1)
56
57#define CTLI_INTCNT_DIS (0 << 1)
58#define CTLI_INTCNT_NE (1 << 1)
59#define CTLI_INTCNT_PE (2 << 1)
60#define CTLI_INTCNT_BE (3 << 1)
61

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304 unsigned int pending, virq, gpio, mask, offset;
305 u8 p[2];
306
307 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
308 dev_err(wg->dev, "Failed to read irq status register\n");
309 return IRQ_NONE;
310 }
311
56#define UPDATE_IRQ_TYPE BIT(0)
57#define UPDATE_IRQ_MASK BIT(1)
58
59#define CTLI_INTCNT_DIS (0 << 1)
60#define CTLI_INTCNT_NE (1 << 1)
61#define CTLI_INTCNT_PE (2 << 1)
62#define CTLI_INTCNT_BE (3 << 1)
63

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306 unsigned int pending, virq, gpio, mask, offset;
307 u8 p[2];
308
309 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
310 dev_err(wg->dev, "Failed to read irq status register\n");
311 return IRQ_NONE;
312 }
313
312 pending = p[0] | (p[1] << 8);
314 pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
313 if (!pending)
314 return IRQ_NONE;
315
316 /* Iterate until no interrupt is pending */
317 while (pending) {
318 /* One iteration is for all pending bits */
319 for_each_set_bit(gpio, (const unsigned long *)&pending,
315 if (!pending)
316 return IRQ_NONE;
317
318 /* Iterate until no interrupt is pending */
319 while (pending) {
320 /* One iteration is for all pending bits */
321 for_each_set_bit(gpio, (const unsigned long *)&pending,
320 GROUP0_NR_IRQS) {
322 WCOVE_GPIO_NUM) {
321 offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0;
322 mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) :
323 BIT(gpio);
324 virq = irq_find_mapping(wg->chip.irqdomain, gpio);
325 handle_nested_irq(virq);
326 regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
327 mask, mask);
328 }
329
330 /* Next iteration */
331 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
332 dev_err(wg->dev, "Failed to read irq status\n");
333 break;
334 }
335
323 offset = (gpio > GROUP0_NR_IRQS) ? 1 : 0;
324 mask = (offset == 1) ? BIT(gpio - GROUP0_NR_IRQS) :
325 BIT(gpio);
326 virq = irq_find_mapping(wg->chip.irqdomain, gpio);
327 handle_nested_irq(virq);
328 regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset,
329 mask, mask);
330 }
331
332 /* Next iteration */
333 if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) {
334 dev_err(wg->dev, "Failed to read irq status\n");
335 break;
336 }
337
336 pending = p[0] | (p[1] << 8);
338 pending = (p[0] & GPIO_IRQ0_MASK) | ((p[1] & GPIO_IRQ1_MASK) << 7);
337 }
338
339 return IRQ_HANDLED;
340}
341
342static void wcove_gpio_dbg_show(struct seq_file *s,
343 struct gpio_chip *chip)
344{

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340
341 return IRQ_HANDLED;
342}
343
344static void wcove_gpio_dbg_show(struct seq_file *s,
345 struct gpio_chip *chip)
346{

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