gpio-tc3589x.c (5c81f2078b7be63be49916128cc86bc17be7f348) gpio-tc3589x.c (cf42f1cfe419f20425fc0c27b9930b6b51fe77b2)
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
6 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
7 */
8
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/slab.h>
13#include <linux/gpio.h>
14#include <linux/of.h>
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
6 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
7 */
8
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/slab.h>
13#include <linux/gpio.h>
14#include <linux/of.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/interrupt.h>
18#include <linux/mfd/tc3589x.h>
19
20/*
21 * These registers are modified under the irq bus lock and cached to avoid
22 * unnecessary writes in bus_sync_unlock.
23 */
24enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
25
26#define CACHE_NR_REGS 4
27#define CACHE_NR_BANKS 3
28
29struct tc3589x_gpio {
30 struct gpio_chip chip;
31 struct tc3589x *tc3589x;
32 struct device *dev;
33 struct mutex irq_lock;
15#include <linux/interrupt.h>
16#include <linux/mfd/tc3589x.h>
17
18/*
19 * These registers are modified under the irq bus lock and cached to avoid
20 * unnecessary writes in bus_sync_unlock.
21 */
22enum { REG_IBE, REG_IEV, REG_IS, REG_IE };
23
24#define CACHE_NR_REGS 4
25#define CACHE_NR_BANKS 3
26
27struct tc3589x_gpio {
28 struct gpio_chip chip;
29 struct tc3589x *tc3589x;
30 struct device *dev;
31 struct mutex irq_lock;
34 struct irq_domain *domain;
35 /* Caches of interrupt control registers for bus_lock */
36 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
37 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
38};
39
40static inline struct tc3589x_gpio *to_tc3589x_gpio(struct gpio_chip *chip)
41{
42 return container_of(chip, struct tc3589x_gpio, chip);

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87 struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
88 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
89 u8 reg = TC3589x_GPIODIR0 + offset / 8;
90 unsigned pos = offset % 8;
91
92 return tc3589x_set_bits(tc3589x, reg, 1 << pos, 0);
93}
94
32 /* Caches of interrupt control registers for bus_lock */
33 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
34 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
35};
36
37static inline struct tc3589x_gpio *to_tc3589x_gpio(struct gpio_chip *chip)
38{
39 return container_of(chip, struct tc3589x_gpio, chip);

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84 struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
85 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
86 u8 reg = TC3589x_GPIODIR0 + offset / 8;
87 unsigned pos = offset % 8;
88
89 return tc3589x_set_bits(tc3589x, reg, 1 << pos, 0);
90}
91
95/**
96 * tc3589x_gpio_irq_get_irq(): Map a hardware IRQ on a chip to a Linux IRQ
97 *
98 * @tc3589x_gpio: tc3589x_gpio_irq controller to operate on.
99 * @irq: index of the hardware interrupt requested in the chip IRQs
100 *
101 * Useful for drivers to request their own IRQs.
102 */
103static int tc3589x_gpio_irq_get_irq(struct tc3589x_gpio *tc3589x_gpio,
104 int hwirq)
105{
106 if (!tc3589x_gpio)
107 return -EINVAL;
108
109 return irq_create_mapping(tc3589x_gpio->domain, hwirq);
110}
111
112static int tc3589x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
113{
114 struct tc3589x_gpio *tc3589x_gpio = to_tc3589x_gpio(chip);
115
116 return tc3589x_gpio_irq_get_irq(tc3589x_gpio, offset);
117}
118
119static struct gpio_chip template_chip = {
120 .label = "tc3589x",
121 .owner = THIS_MODULE,
122 .direction_input = tc3589x_gpio_direction_input,
123 .get = tc3589x_gpio_get,
124 .direction_output = tc3589x_gpio_direction_output,
125 .set = tc3589x_gpio_set,
92static struct gpio_chip template_chip = {
93 .label = "tc3589x",
94 .owner = THIS_MODULE,
95 .direction_input = tc3589x_gpio_direction_input,
96 .get = tc3589x_gpio_get,
97 .direction_output = tc3589x_gpio_direction_output,
98 .set = tc3589x_gpio_set,
126 .to_irq = tc3589x_gpio_to_irq,
127 .can_sleep = true,
128};
129
130static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
131{
99 .can_sleep = true,
100};
101
102static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
103{
132 struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
104 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
105 struct tc3589x_gpio *tc3589x_gpio = container_of(gc, struct tc3589x_gpio, chip);
133 int offset = d->hwirq;
134 int regoffset = offset / 8;
135 int mask = 1 << (offset % 8);
136
137 if (type == IRQ_TYPE_EDGE_BOTH) {
138 tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
139 return 0;
140 }

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151 else
152 tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
153
154 return 0;
155}
156
157static void tc3589x_gpio_irq_lock(struct irq_data *d)
158{
106 int offset = d->hwirq;
107 int regoffset = offset / 8;
108 int mask = 1 << (offset % 8);
109
110 if (type == IRQ_TYPE_EDGE_BOTH) {
111 tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
112 return 0;
113 }

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124 else
125 tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
126
127 return 0;
128}
129
130static void tc3589x_gpio_irq_lock(struct irq_data *d)
131{
159 struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
132 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
133 struct tc3589x_gpio *tc3589x_gpio = container_of(gc, struct tc3589x_gpio, chip);
160
161 mutex_lock(&tc3589x_gpio->irq_lock);
162}
163
164static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
165{
134
135 mutex_lock(&tc3589x_gpio->irq_lock);
136}
137
138static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
139{
166 struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
140 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
141 struct tc3589x_gpio *tc3589x_gpio = container_of(gc, struct tc3589x_gpio, chip);
167 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
168 static const u8 regmap[] = {
169 [REG_IBE] = TC3589x_GPIOIBE0,
170 [REG_IEV] = TC3589x_GPIOIEV0,
171 [REG_IS] = TC3589x_GPIOIS0,
172 [REG_IE] = TC3589x_GPIOIE0,
173 };
174 int i, j;

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186 }
187 }
188
189 mutex_unlock(&tc3589x_gpio->irq_lock);
190}
191
192static void tc3589x_gpio_irq_mask(struct irq_data *d)
193{
142 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
143 static const u8 regmap[] = {
144 [REG_IBE] = TC3589x_GPIOIBE0,
145 [REG_IEV] = TC3589x_GPIOIEV0,
146 [REG_IS] = TC3589x_GPIOIS0,
147 [REG_IE] = TC3589x_GPIOIE0,
148 };
149 int i, j;

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161 }
162 }
163
164 mutex_unlock(&tc3589x_gpio->irq_lock);
165}
166
167static void tc3589x_gpio_irq_mask(struct irq_data *d)
168{
194 struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
169 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
170 struct tc3589x_gpio *tc3589x_gpio = container_of(gc, struct tc3589x_gpio, chip);
195 int offset = d->hwirq;
196 int regoffset = offset / 8;
197 int mask = 1 << (offset % 8);
198
199 tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
200}
201
202static void tc3589x_gpio_irq_unmask(struct irq_data *d)
203{
171 int offset = d->hwirq;
172 int regoffset = offset / 8;
173 int mask = 1 << (offset % 8);
174
175 tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
176}
177
178static void tc3589x_gpio_irq_unmask(struct irq_data *d)
179{
204 struct tc3589x_gpio *tc3589x_gpio = irq_data_get_irq_chip_data(d);
180 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
181 struct tc3589x_gpio *tc3589x_gpio = container_of(gc, struct tc3589x_gpio, chip);
205 int offset = d->hwirq;
206 int regoffset = offset / 8;
207 int mask = 1 << (offset % 8);
208
209 tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
210}
211
212static struct irq_chip tc3589x_gpio_irq_chip = {

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234 for (i = 0; i < ARRAY_SIZE(status); i++) {
235 unsigned int stat = status[i];
236 if (!stat)
237 continue;
238
239 while (stat) {
240 int bit = __ffs(stat);
241 int line = i * 8 + bit;
182 int offset = d->hwirq;
183 int regoffset = offset / 8;
184 int mask = 1 << (offset % 8);
185
186 tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
187}
188
189static struct irq_chip tc3589x_gpio_irq_chip = {

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211 for (i = 0; i < ARRAY_SIZE(status); i++) {
212 unsigned int stat = status[i];
213 if (!stat)
214 continue;
215
216 while (stat) {
217 int bit = __ffs(stat);
218 int line = i * 8 + bit;
242 int irq = tc3589x_gpio_irq_get_irq(tc3589x_gpio, line);
219 int irq = irq_find_mapping(tc3589x_gpio->chip.irqdomain,
220 line);
243
244 handle_nested_irq(irq);
245 stat &= ~(1 << bit);
246 }
247
248 tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
249 }
250
251 return IRQ_HANDLED;
252}
253
221
222 handle_nested_irq(irq);
223 stat &= ~(1 << bit);
224 }
225
226 tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
227 }
228
229 return IRQ_HANDLED;
230}
231
254static int tc3589x_gpio_irq_map(struct irq_domain *d, unsigned int irq,
255 irq_hw_number_t hwirq)
256{
257 struct tc3589x *tc3589x_gpio = d->host_data;
258
259 irq_set_chip_data(irq, tc3589x_gpio);
260 irq_set_chip_and_handler(irq, &tc3589x_gpio_irq_chip,
261 handle_simple_irq);
262 irq_set_nested_thread(irq, 1);
263#ifdef CONFIG_ARM
264 set_irq_flags(irq, IRQF_VALID);
265#else
266 irq_set_noprobe(irq);
267#endif
268
269 return 0;
270}
271
272static void tc3589x_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
273{
274#ifdef CONFIG_ARM
275 set_irq_flags(irq, 0);
276#endif
277 irq_set_chip_and_handler(irq, NULL, NULL);
278 irq_set_chip_data(irq, NULL);
279}
280
281static struct irq_domain_ops tc3589x_irq_ops = {
282 .map = tc3589x_gpio_irq_map,
283 .unmap = tc3589x_gpio_irq_unmap,
284 .xlate = irq_domain_xlate_twocell,
285};
286
287static int tc3589x_gpio_irq_init(struct tc3589x_gpio *tc3589x_gpio,
288 struct device_node *np)
289{
290 /*
291 * If this results in a linear domain, irq_create_mapping() will
292 * take care of allocating IRQ descriptors at runtime. When a base
293 * is provided, the IRQ descriptors will be allocated when the
294 * domain is instantiated.
295 */
296 tc3589x_gpio->domain = irq_domain_add_simple(np,
297 tc3589x_gpio->chip.ngpio, 0, &tc3589x_irq_ops,
298 tc3589x_gpio);
299 if (!tc3589x_gpio->domain) {
300 dev_err(tc3589x_gpio->dev, "Failed to create irqdomain\n");
301 return -ENOSYS;
302 }
303
304 return 0;
305}
306
307static int tc3589x_gpio_probe(struct platform_device *pdev)
308{
309 struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
310 struct tc3589x_gpio_platform_data *pdata;
311 struct device_node *np = pdev->dev.of_node;
312 struct tc3589x_gpio *tc3589x_gpio;
313 int ret;
314 int irq;

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344#endif
345
346 /* Bring the GPIO module out of reset */
347 ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
348 TC3589x_RSTCTRL_GPIRST, 0);
349 if (ret < 0)
350 return ret;
351
232static int tc3589x_gpio_probe(struct platform_device *pdev)
233{
234 struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
235 struct tc3589x_gpio_platform_data *pdata;
236 struct device_node *np = pdev->dev.of_node;
237 struct tc3589x_gpio *tc3589x_gpio;
238 int ret;
239 int irq;

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269#endif
270
271 /* Bring the GPIO module out of reset */
272 ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
273 TC3589x_RSTCTRL_GPIRST, 0);
274 if (ret < 0)
275 return ret;
276
352 ret = tc3589x_gpio_irq_init(tc3589x_gpio, np);
353 if (ret)
354 return ret;
355
356 ret = devm_request_threaded_irq(&pdev->dev,
357 irq, NULL, tc3589x_gpio_irq,
358 IRQF_ONESHOT, "tc3589x-gpio",
359 tc3589x_gpio);
360 if (ret) {
361 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
362 return ret;
363 }
364
365 ret = gpiochip_add(&tc3589x_gpio->chip);
366 if (ret) {
367 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
368 return ret;
369 }
370
277 ret = devm_request_threaded_irq(&pdev->dev,
278 irq, NULL, tc3589x_gpio_irq,
279 IRQF_ONESHOT, "tc3589x-gpio",
280 tc3589x_gpio);
281 if (ret) {
282 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
283 return ret;
284 }
285
286 ret = gpiochip_add(&tc3589x_gpio->chip);
287 if (ret) {
288 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
289 return ret;
290 }
291
292 ret = gpiochip_irqchip_add(&tc3589x_gpio->chip,
293 &tc3589x_gpio_irq_chip,
294 0,
295 handle_simple_irq,
296 IRQ_TYPE_NONE);
297 if (ret) {
298 dev_err(&pdev->dev,
299 "could not connect irqchip to gpiochip\n");
300 return ret;
301 }
302
371 if (pdata && pdata->setup)
372 pdata->setup(tc3589x, tc3589x_gpio->chip.base);
373
374 platform_set_drvdata(pdev, tc3589x_gpio);
375
376 return 0;
377}
378

--- 42 unchanged lines hidden --- 		303 if (pdata && pdata->setup)
304 pdata->setup(tc3589x, tc3589x_gpio->chip.base);
305
306 platform_set_drvdata(pdev, tc3589x_gpio);
307
308 return 0;
309}
310

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