gpio-stmpe.c (03ab3da3b215bac4ebb093c808d54596e03e3225) gpio-stmpe.c (fe44e70db0544e24cd1d00fc594b6e5b0afd333b)
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/gpio.h>
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
6 */
7
8#include <linux/module.h>
9#include <linux/init.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/gpio.h>
13#include <linux/irq.h>
14#include <linux/irqdomain.h>
15#include <linux/interrupt.h>
16#include <linux/of.h>
17#include <linux/mfd/stmpe.h>
18
19/*
20 * These registers are modified under the irq bus lock and cached to avoid
21 * unnecessary writes in bus_sync_unlock.
22 */
23enum { REG_RE, REG_FE, REG_IE };
24
25#define CACHE_NR_REGS 3
26/* No variant has more than 24 GPIOs */
27#define CACHE_NR_BANKS (24 / 8)
28
29struct stmpe_gpio {
30 struct gpio_chip chip;
31 struct stmpe *stmpe;
32 struct device *dev;
33 struct mutex irq_lock;
13#include <linux/interrupt.h>
14#include <linux/of.h>
15#include <linux/mfd/stmpe.h>
16
17/*
18 * These registers are modified under the irq bus lock and cached to avoid
19 * unnecessary writes in bus_sync_unlock.
20 */
21enum { REG_RE, REG_FE, REG_IE };
22
23#define CACHE_NR_REGS 3
24/* No variant has more than 24 GPIOs */
25#define CACHE_NR_BANKS (24 / 8)
26
27struct stmpe_gpio {
28 struct gpio_chip chip;
29 struct stmpe *stmpe;
30 struct device *dev;
31 struct mutex irq_lock;
34 struct irq_domain *domain;
35 unsigned norequest_mask;
32 unsigned norequest_mask;
36
37 /* Caches of interrupt control registers for bus_lock */
38 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
39 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
40};
41
42static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
43{
44 return container_of(chip, struct stmpe_gpio, chip);

--- 51 unchanged lines hidden (view full) ---

96 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
97 struct stmpe *stmpe = stmpe_gpio->stmpe;
98 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
99 u8 mask = 1 << (offset % 8);
100
101 return stmpe_set_bits(stmpe, reg, mask, 0);
102}
103
33 /* Caches of interrupt control registers for bus_lock */
34 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
35 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
36};
37
38static inline struct stmpe_gpio *to_stmpe_gpio(struct gpio_chip *chip)
39{
40 return container_of(chip, struct stmpe_gpio, chip);

--- 51 unchanged lines hidden (view full) ---

92 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
93 struct stmpe *stmpe = stmpe_gpio->stmpe;
94 u8 reg = stmpe->regs[STMPE_IDX_GPDR_LSB] - (offset / 8);
95 u8 mask = 1 << (offset % 8);
96
97 return stmpe_set_bits(stmpe, reg, mask, 0);
98}
99
104static int stmpe_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
105{
106 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
107
108 return irq_create_mapping(stmpe_gpio->domain, offset);
109}
110
111static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
112{
113 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
114 struct stmpe *stmpe = stmpe_gpio->stmpe;
115
116 if (stmpe_gpio->norequest_mask & (1 << offset))
117 return -EINVAL;
118
119 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
120}
121
122static struct gpio_chip template_chip = {
123 .label = "stmpe",
124 .owner = THIS_MODULE,
125 .direction_input = stmpe_gpio_direction_input,
126 .get = stmpe_gpio_get,
127 .direction_output = stmpe_gpio_direction_output,
128 .set = stmpe_gpio_set,
100static int stmpe_gpio_request(struct gpio_chip *chip, unsigned offset)
101{
102 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(chip);
103 struct stmpe *stmpe = stmpe_gpio->stmpe;
104
105 if (stmpe_gpio->norequest_mask & (1 << offset))
106 return -EINVAL;
107
108 return stmpe_set_altfunc(stmpe, 1 << offset, STMPE_BLOCK_GPIO);
109}
110
111static struct gpio_chip template_chip = {
112 .label = "stmpe",
113 .owner = THIS_MODULE,
114 .direction_input = stmpe_gpio_direction_input,
115 .get = stmpe_gpio_get,
116 .direction_output = stmpe_gpio_direction_output,
117 .set = stmpe_gpio_set,
129 .to_irq = stmpe_gpio_to_irq,
130 .request = stmpe_gpio_request,
131 .can_sleep = true,
132};
133
134static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
135{
118 .request = stmpe_gpio_request,
119 .can_sleep = true,
120};
121
122static int stmpe_gpio_irq_set_type(struct irq_data *d, unsigned int type)
123{
136 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
124 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
125 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
137 int offset = d->hwirq;
138 int regoffset = offset / 8;
139 int mask = 1 << (offset % 8);
140
141 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
142 return -EINVAL;
143
144 /* STMPE801 doesn't have RE and FE registers */

--- 10 unchanged lines hidden (view full) ---

155 else
156 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
157
158 return 0;
159}
160
161static void stmpe_gpio_irq_lock(struct irq_data *d)
162{
126 int offset = d->hwirq;
127 int regoffset = offset / 8;
128 int mask = 1 << (offset % 8);
129
130 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
131 return -EINVAL;
132
133 /* STMPE801 doesn't have RE and FE registers */

--- 10 unchanged lines hidden (view full) ---

144 else
145 stmpe_gpio->regs[REG_FE][regoffset] &= ~mask;
146
147 return 0;
148}
149
150static void stmpe_gpio_irq_lock(struct irq_data *d)
151{
163 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
152 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
153 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
164
165 mutex_lock(&stmpe_gpio->irq_lock);
166}
167
168static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
169{
154
155 mutex_lock(&stmpe_gpio->irq_lock);
156}
157
158static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
159{
170 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
160 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
161 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
171 struct stmpe *stmpe = stmpe_gpio->stmpe;
172 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
173 static const u8 regmap[] = {
174 [REG_RE] = STMPE_IDX_GPRER_LSB,
175 [REG_FE] = STMPE_IDX_GPFER_LSB,
176 [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
177 };
178 int i, j;

--- 16 unchanged lines hidden (view full) ---

195 }
196 }
197
198 mutex_unlock(&stmpe_gpio->irq_lock);
199}
200
201static void stmpe_gpio_irq_mask(struct irq_data *d)
202{
162 struct stmpe *stmpe = stmpe_gpio->stmpe;
163 int num_banks = DIV_ROUND_UP(stmpe->num_gpios, 8);
164 static const u8 regmap[] = {
165 [REG_RE] = STMPE_IDX_GPRER_LSB,
166 [REG_FE] = STMPE_IDX_GPFER_LSB,
167 [REG_IE] = STMPE_IDX_IEGPIOR_LSB,
168 };
169 int i, j;

--- 16 unchanged lines hidden (view full) ---

186 }
187 }
188
189 mutex_unlock(&stmpe_gpio->irq_lock);
190}
191
192static void stmpe_gpio_irq_mask(struct irq_data *d)
193{
203 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
194 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
195 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
204 int offset = d->hwirq;
205 int regoffset = offset / 8;
206 int mask = 1 << (offset % 8);
207
208 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
209}
210
211static void stmpe_gpio_irq_unmask(struct irq_data *d)
212{
196 int offset = d->hwirq;
197 int regoffset = offset / 8;
198 int mask = 1 << (offset % 8);
199
200 stmpe_gpio->regs[REG_IE][regoffset] &= ~mask;
201}
202
203static void stmpe_gpio_irq_unmask(struct irq_data *d)
204{
213 struct stmpe_gpio *stmpe_gpio = irq_data_get_irq_chip_data(d);
205 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
206 struct stmpe_gpio *stmpe_gpio = to_stmpe_gpio(gc);
214 int offset = d->hwirq;
215 int regoffset = offset / 8;
216 int mask = 1 << (offset % 8);
217
218 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
219}
220
221static struct irq_chip stmpe_gpio_irq_chip = {

--- 26 unchanged lines hidden (view full) ---

248
249 stat &= enabled;
250 if (!stat)
251 continue;
252
253 while (stat) {
254 int bit = __ffs(stat);
255 int line = bank * 8 + bit;
207 int offset = d->hwirq;
208 int regoffset = offset / 8;
209 int mask = 1 << (offset % 8);
210
211 stmpe_gpio->regs[REG_IE][regoffset] |= mask;
212}
213
214static struct irq_chip stmpe_gpio_irq_chip = {

--- 26 unchanged lines hidden (view full) ---

241
242 stat &= enabled;
243 if (!stat)
244 continue;
245
246 while (stat) {
247 int bit = __ffs(stat);
248 int line = bank * 8 + bit;
256 int child_irq = irq_find_mapping(stmpe_gpio->domain,
249 int child_irq = irq_find_mapping(stmpe_gpio->chip.irqdomain,
257 line);
258
259 handle_nested_irq(child_irq);
260 stat &= ~(1 << bit);
261 }
262
263 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
264
265 /* Edge detect register is not present on 801 */
266 if (stmpe->partnum != STMPE801)
267 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
268 + i, status[i]);
269 }
270
271 return IRQ_HANDLED;
272}
273
250 line);
251
252 handle_nested_irq(child_irq);
253 stat &= ~(1 << bit);
254 }
255
256 stmpe_reg_write(stmpe, statmsbreg + i, status[i]);
257
258 /* Edge detect register is not present on 801 */
259 if (stmpe->partnum != STMPE801)
260 stmpe_reg_write(stmpe, stmpe->regs[STMPE_IDX_GPEDR_MSB]
261 + i, status[i]);
262 }
263
264 return IRQ_HANDLED;
265}
266
274static int stmpe_gpio_irq_map(struct irq_domain *d, unsigned int irq,
275 irq_hw_number_t hwirq)
276{
277 struct stmpe_gpio *stmpe_gpio = d->host_data;
278
279 if (!stmpe_gpio)
280 return -EINVAL;
281
282 irq_set_chip_data(irq, stmpe_gpio);
283 irq_set_chip_and_handler(irq, &stmpe_gpio_irq_chip,
284 handle_simple_irq);
285 irq_set_nested_thread(irq, 1);
286#ifdef CONFIG_ARM
287 set_irq_flags(irq, IRQF_VALID);
288#else
289 irq_set_noprobe(irq);
290#endif
291
292 return 0;
293}
294
295static void stmpe_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
296{
297#ifdef CONFIG_ARM
298 set_irq_flags(irq, 0);
299#endif
300 irq_set_chip_and_handler(irq, NULL, NULL);
301 irq_set_chip_data(irq, NULL);
302}
303
304static const struct irq_domain_ops stmpe_gpio_irq_simple_ops = {
305 .unmap = stmpe_gpio_irq_unmap,
306 .map = stmpe_gpio_irq_map,
307 .xlate = irq_domain_xlate_twocell,
308};
309
310static int stmpe_gpio_irq_init(struct stmpe_gpio *stmpe_gpio,
311 struct device_node *np)
312{
313 stmpe_gpio->domain = irq_domain_add_simple(np,
314 stmpe_gpio->chip.ngpio, 0,
315 &stmpe_gpio_irq_simple_ops, stmpe_gpio);
316 if (!stmpe_gpio->domain) {
317 dev_err(stmpe_gpio->dev, "failed to create irqdomain\n");
318 return -ENOSYS;
319 }
320
321 return 0;
322}
323
324static int stmpe_gpio_probe(struct platform_device *pdev)
325{
326 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
327 struct device_node *np = pdev->dev.of_node;
328 struct stmpe_gpio_platform_data *pdata;
329 struct stmpe_gpio *stmpe_gpio;
330 int ret;
331 int irq = 0;

--- 21 unchanged lines hidden (view full) ---

353 if (pdata)
354 stmpe_gpio->norequest_mask = pdata->norequest_mask;
355 else if (np)
356 of_property_read_u32(np, "st,norequest-mask",
357 &stmpe_gpio->norequest_mask);
358
359 if (irq < 0)
360 dev_info(&pdev->dev,
267static int stmpe_gpio_probe(struct platform_device *pdev)
268{
269 struct stmpe *stmpe = dev_get_drvdata(pdev->dev.parent);
270 struct device_node *np = pdev->dev.of_node;
271 struct stmpe_gpio_platform_data *pdata;
272 struct stmpe_gpio *stmpe_gpio;
273 int ret;
274 int irq = 0;

--- 21 unchanged lines hidden (view full) ---

296 if (pdata)
297 stmpe_gpio->norequest_mask = pdata->norequest_mask;
298 else if (np)
299 of_property_read_u32(np, "st,norequest-mask",
300 &stmpe_gpio->norequest_mask);
301
302 if (irq < 0)
303 dev_info(&pdev->dev,
361 "device configured in no-irq mode; "
304 "device configured in no-irq mode: "
362 "irqs are not available\n");
363
364 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
365 if (ret)
366 goto out_free;
367
305 "irqs are not available\n");
306
307 ret = stmpe_enable(stmpe, STMPE_BLOCK_GPIO);
308 if (ret)
309 goto out_free;
310
368 if (irq >= 0) {
369 ret = stmpe_gpio_irq_init(stmpe_gpio, np);
370 if (ret)
371 goto out_disable;
372
373 ret = request_threaded_irq(irq, NULL, stmpe_gpio_irq,
374 IRQF_ONESHOT, "stmpe-gpio", stmpe_gpio);
311 if (irq > 0) {
312 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
313 stmpe_gpio_irq, IRQF_ONESHOT,
314 "stmpe-gpio", stmpe_gpio);
375 if (ret) {
376 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
377 goto out_disable;
378 }
315 if (ret) {
316 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
317 goto out_disable;
318 }
319 ret = gpiochip_irqchip_add(&stmpe_gpio->chip,
320 &stmpe_gpio_irq_chip,
321 0,
322 handle_simple_irq,
323 IRQ_TYPE_NONE);
324 if (ret) {
325 dev_err(&pdev->dev,
326 "could not connect irqchip to gpiochip\n");
327 return ret;
328 }
379 }
380
381 ret = gpiochip_add(&stmpe_gpio->chip);
382 if (ret) {
383 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
329 }
330
331 ret = gpiochip_add(&stmpe_gpio->chip);
332 if (ret) {
333 dev_err(&pdev->dev, "unable to add gpiochip: %d\n", ret);
384 goto out_freeirq;
334 goto out_disable;
385 }
386
387 if (pdata && pdata->setup)
388 pdata->setup(stmpe, stmpe_gpio->chip.base);
389
390 platform_set_drvdata(pdev, stmpe_gpio);
391
392 return 0;
393
335 }
336
337 if (pdata && pdata->setup)
338 pdata->setup(stmpe, stmpe_gpio->chip.base);
339
340 platform_set_drvdata(pdev, stmpe_gpio);
341
342 return 0;
343
394out_freeirq:
395 if (irq >= 0)
396 free_irq(irq, stmpe_gpio);
397out_disable:
398 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
399out_free:
400 kfree(stmpe_gpio);
401 return ret;
402}
403
404static int stmpe_gpio_remove(struct platform_device *pdev)
405{
406 struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
407 struct stmpe *stmpe = stmpe_gpio->stmpe;
408 struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
344out_disable:
345 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
346out_free:
347 kfree(stmpe_gpio);
348 return ret;
349}
350
351static int stmpe_gpio_remove(struct platform_device *pdev)
352{
353 struct stmpe_gpio *stmpe_gpio = platform_get_drvdata(pdev);
354 struct stmpe *stmpe = stmpe_gpio->stmpe;
355 struct stmpe_gpio_platform_data *pdata = stmpe->pdata->gpio;
409 int irq = platform_get_irq(pdev, 0);
410 int ret;
411
412 if (pdata && pdata->remove)
413 pdata->remove(stmpe, stmpe_gpio->chip.base);
414
415 ret = gpiochip_remove(&stmpe_gpio->chip);
416 if (ret < 0) {
417 dev_err(stmpe_gpio->dev,
418 "unable to remove gpiochip: %d\n", ret);
419 return ret;
420 }
421
422 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
423
356 int ret;
357
358 if (pdata && pdata->remove)
359 pdata->remove(stmpe, stmpe_gpio->chip.base);
360
361 ret = gpiochip_remove(&stmpe_gpio->chip);
362 if (ret < 0) {
363 dev_err(stmpe_gpio->dev,
364 "unable to remove gpiochip: %d\n", ret);
365 return ret;
366 }
367
368 stmpe_disable(stmpe, STMPE_BLOCK_GPIO);
369
424 if (irq >= 0)
425 free_irq(irq, stmpe_gpio);
426
427 kfree(stmpe_gpio);
428
429 return 0;
430}
431
432static struct platform_driver stmpe_gpio_driver = {
433 .driver.name = "stmpe-gpio",
434 .driver.owner = THIS_MODULE,

--- 19 unchanged lines hidden --- 		370 kfree(stmpe_gpio);
371
372 return 0;
373}
374
375static struct platform_driver stmpe_gpio_driver = {
376 .driver.name = "stmpe-gpio",
377 .driver.owner = THIS_MODULE,

--- 19 unchanged lines hidden ---