gpio-sodaville.c (6ac1ef482d7ae0c690f1640bf6eb818ff9a2d91e) gpio-sodaville.c (d5efccd5b6843c504042735c1e20d9252daefd98)
1/*
2 * GPIO interface for Intel Sodaville SoCs.
3 *
4 * Copyright (c) 2010, 2011 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License 2 as published
8 * by the Free Software Foundation.

--- 27 unchanged lines hidden (view full) ---

36#define GPIO_INT 0x14
37#define GPIT1R1 0x18
38
39#define GPMUXCTL 0x1c
40
41struct sdv_gpio_chip_data {
42 int irq_base;
43 void __iomem *gpio_pub_base;
1/*
2 * GPIO interface for Intel Sodaville SoCs.
3 *
4 * Copyright (c) 2010, 2011 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License 2 as published
8 * by the Free Software Foundation.

--- 27 unchanged lines hidden (view full) ---

36#define GPIO_INT 0x14
37#define GPIT1R1 0x18
38
39#define GPMUXCTL 0x1c
40
41struct sdv_gpio_chip_data {
42 int irq_base;
43 void __iomem *gpio_pub_base;
44 struct irq_domain id;
44 struct irq_domain *id;
45 struct irq_chip_generic *gc;
46 struct bgpio_chip bgpio;
47};
48
49static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
50{
51 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
52 struct sdv_gpio_chip_data *sd = gc->private;
53 void __iomem *type_reg;
45 struct irq_chip_generic *gc;
46 struct bgpio_chip bgpio;
47};
48
49static int sdv_gpio_pub_set_type(struct irq_data *d, unsigned int type)
50{
51 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
52 struct sdv_gpio_chip_data *sd = gc->private;
53 void __iomem *type_reg;
54 u32 irq_offs = d->irq - sd->irq_base;
55 u32 reg;
56
54 u32 reg;
55
57 if (irq_offs < 8)
56 if (d->hwirq < 8)
58 type_reg = sd->gpio_pub_base + GPIT1R0;
59 else
60 type_reg = sd->gpio_pub_base + GPIT1R1;
61
62 reg = readl(type_reg);
63
64 switch (type) {
65 case IRQ_TYPE_LEVEL_HIGH:
57 type_reg = sd->gpio_pub_base + GPIT1R0;
58 else
59 type_reg = sd->gpio_pub_base + GPIT1R1;
60
61 reg = readl(type_reg);
62
63 switch (type) {
64 case IRQ_TYPE_LEVEL_HIGH:
66 reg &= ~BIT(4 * (irq_offs % 8));
65 reg &= ~BIT(4 * (d->hwirq % 8));
67 break;
68
69 case IRQ_TYPE_LEVEL_LOW:
66 break;
67
68 case IRQ_TYPE_LEVEL_LOW:
70 reg |= BIT(4 * (irq_offs % 8));
69 reg |= BIT(4 * (d->hwirq % 8));
71 break;
72
73 default:
74 return -EINVAL;
75 }
76
77 writel(reg, type_reg);
78 return 0;

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86 irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
87 if (!irq_stat)
88 return IRQ_NONE;
89
90 while (irq_stat) {
91 u32 irq_bit = __fls(irq_stat);
92
93 irq_stat &= ~BIT(irq_bit);
70 break;
71
72 default:
73 return -EINVAL;
74 }
75
76 writel(reg, type_reg);
77 return 0;

--- 7 unchanged lines hidden (view full) ---

85 irq_stat &= readl(sd->gpio_pub_base + GPIO_INT);
86 if (!irq_stat)
87 return IRQ_NONE;
88
89 while (irq_stat) {
90 u32 irq_bit = __fls(irq_stat);
91
92 irq_stat &= ~BIT(irq_bit);
94 generic_handle_irq(sd->irq_base + irq_bit);
93 generic_handle_irq(irq_find_mapping(sd->id, irq_bit));
95 }
96
97 return IRQ_HANDLED;
98}
99
100static int sdv_xlate(struct irq_domain *h, struct device_node *node,
101 const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
102 u32 *out_type)

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122 break;
123 default:
124 return -EINVAL;
125 }
126 return 0;
127}
128
129static struct irq_domain_ops irq_domain_sdv_ops = {
94 }
95
96 return IRQ_HANDLED;
97}
98
99static int sdv_xlate(struct irq_domain *h, struct device_node *node,
100 const u32 *intspec, u32 intsize, irq_hw_number_t *out_hwirq,
101 u32 *out_type)

--- 19 unchanged lines hidden (view full) ---

121 break;
122 default:
123 return -EINVAL;
124 }
125 return 0;
126}
127
128static struct irq_domain_ops irq_domain_sdv_ops = {
130 .dt_translate = sdv_xlate,
129 .xlate = sdv_xlate,
131};
132
133static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
134 struct pci_dev *pdev)
135{
136 struct irq_chip_type *ct;
137 int ret;
138

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144 writel(0, sd->gpio_pub_base + GPIO_INT);
145 writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
146
147 ret = request_irq(pdev->irq, sdv_gpio_pub_irq_handler, IRQF_SHARED,
148 "sdv_gpio", sd);
149 if (ret)
150 goto out_free_desc;
151
130};
131
132static __devinit int sdv_register_irqsupport(struct sdv_gpio_chip_data *sd,
133 struct pci_dev *pdev)
134{
135 struct irq_chip_type *ct;
136 int ret;
137

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143 writel(0, sd->gpio_pub_base + GPIO_INT);
144 writel((1 << 11) - 1, sd->gpio_pub_base + GPSTR);
145
146 ret = request_irq(pdev->irq, sdv_gpio_pub_irq_handler, IRQF_SHARED,
147 "sdv_gpio", sd);
148 if (ret)
149 goto out_free_desc;
150
152 sd->id.irq_base = sd->irq_base;
153 sd->id.of_node = of_node_get(pdev->dev.of_node);
154 sd->id.ops = &irq_domain_sdv_ops;
155
156 /*
157 * This gpio irq controller latches level irqs. Testing shows that if
158 * we unmask & ACK the IRQ before the source of the interrupt is gone
159 * then the interrupt is active again.
160 */
161 sd->gc = irq_alloc_generic_chip("sdv-gpio", 1, sd->irq_base,
162 sd->gpio_pub_base, handle_fasteoi_irq);
163 if (!sd->gc) {

--- 10 unchanged lines hidden (view full) ---

174 ct->chip.irq_unmask = irq_gc_mask_set_bit;
175 ct->chip.irq_eoi = irq_gc_eoi;
176 ct->chip.irq_set_type = sdv_gpio_pub_set_type;
177
178 irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
179 IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
180 IRQ_LEVEL | IRQ_NOPROBE);
181
151 /*
152 * This gpio irq controller latches level irqs. Testing shows that if
153 * we unmask & ACK the IRQ before the source of the interrupt is gone
154 * then the interrupt is active again.
155 */
156 sd->gc = irq_alloc_generic_chip("sdv-gpio", 1, sd->irq_base,
157 sd->gpio_pub_base, handle_fasteoi_irq);
158 if (!sd->gc) {

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169 ct->chip.irq_unmask = irq_gc_mask_set_bit;
170 ct->chip.irq_eoi = irq_gc_eoi;
171 ct->chip.irq_set_type = sdv_gpio_pub_set_type;
172
173 irq_setup_generic_chip(sd->gc, IRQ_MSK(SDV_NUM_PUB_GPIOS),
174 IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST,
175 IRQ_LEVEL | IRQ_NOPROBE);
176
182 irq_domain_add(&sd->id);
177 sd->id = irq_domain_add_legacy(pdev->dev.of_node, SDV_NUM_PUB_GPIOS,
178 sd->irq_base, 0, &irq_domain_sdv_ops, sd);
179 if (!sd->id)
180 goto out_free_irq;
183 return 0;
184out_free_irq:
185 free_irq(pdev->irq, sd);
186out_free_desc:
187 irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
188 return ret;
189}
190

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255 kfree(sd);
256 return ret;
257}
258
259static void sdv_gpio_remove(struct pci_dev *pdev)
260{
261 struct sdv_gpio_chip_data *sd = pci_get_drvdata(pdev);
262
181 return 0;
182out_free_irq:
183 free_irq(pdev->irq, sd);
184out_free_desc:
185 irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
186 return ret;
187}
188

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253 kfree(sd);
254 return ret;
255}
256
257static void sdv_gpio_remove(struct pci_dev *pdev)
258{
259 struct sdv_gpio_chip_data *sd = pci_get_drvdata(pdev);
260
263 irq_domain_del(&sd->id);
264 free_irq(pdev->irq, sd);
265 irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
266
267 if (gpiochip_remove(&sd->bgpio.gc))
268 dev_err(&pdev->dev, "gpiochip_remove() failed.\n");
269
270 pci_release_region(pdev, GPIO_BAR);
271 iounmap(sd->gpio_pub_base);

--- 31 unchanged lines hidden --- 		261 free_irq(pdev->irq, sd);
262 irq_free_descs(sd->irq_base, SDV_NUM_PUB_GPIOS);
263
264 if (gpiochip_remove(&sd->bgpio.gc))
265 dev_err(&pdev->dev, "gpiochip_remove() failed.\n");
266
267 pci_release_region(pdev, GPIO_BAR);
268 iounmap(sd->gpio_pub_base);

--- 31 unchanged lines hidden ---