gpio-lpc32xx.c (c39f2d9db0fd81ea20bb5cce9b3f082ca63753e2) gpio-lpc32xx.c (f2ee73147a3f23cc4b032a76b5677b4b8441ba74)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * GPIO driver for LPC32xx SoC
4 *
5 * Author: Kevin Wells <kevin.wells@nxp.com>
6 *
7 * Copyright (C) 2010 NXP Semiconductors
8 */
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/errno.h>
14#include <linux/gpio/driver.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/module.h>
18
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * GPIO driver for LPC32xx SoC
4 *
5 * Author: Kevin Wells <kevin.wells@nxp.com>
6 *
7 * Copyright (C) 2010 NXP Semiconductors
8 */
9
10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/io.h>
13#include <linux/errno.h>
14#include <linux/gpio/driver.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/module.h>
18
19#include <mach/hardware.h>
20#include <mach/platform.h>
19#define LPC32XX_GPIO_P3_INP_STATE (0x000)
20#define LPC32XX_GPIO_P3_OUTP_SET (0x004)
21#define LPC32XX_GPIO_P3_OUTP_CLR (0x008)
22#define LPC32XX_GPIO_P3_OUTP_STATE (0x00C)
23#define LPC32XX_GPIO_P2_DIR_SET (0x010)
24#define LPC32XX_GPIO_P2_DIR_CLR (0x014)
25#define LPC32XX_GPIO_P2_DIR_STATE (0x018)
26#define LPC32XX_GPIO_P2_INP_STATE (0x01C)
27#define LPC32XX_GPIO_P2_OUTP_SET (0x020)
28#define LPC32XX_GPIO_P2_OUTP_CLR (0x024)
29#define LPC32XX_GPIO_P2_MUX_SET (0x028)
30#define LPC32XX_GPIO_P2_MUX_CLR (0x02C)
31#define LPC32XX_GPIO_P2_MUX_STATE (0x030)
32#define LPC32XX_GPIO_P0_INP_STATE (0x040)
33#define LPC32XX_GPIO_P0_OUTP_SET (0x044)
34#define LPC32XX_GPIO_P0_OUTP_CLR (0x048)
35#define LPC32XX_GPIO_P0_OUTP_STATE (0x04C)
36#define LPC32XX_GPIO_P0_DIR_SET (0x050)
37#define LPC32XX_GPIO_P0_DIR_CLR (0x054)
38#define LPC32XX_GPIO_P0_DIR_STATE (0x058)
39#define LPC32XX_GPIO_P1_INP_STATE (0x060)
40#define LPC32XX_GPIO_P1_OUTP_SET (0x064)
41#define LPC32XX_GPIO_P1_OUTP_CLR (0x068)
42#define LPC32XX_GPIO_P1_OUTP_STATE (0x06C)
43#define LPC32XX_GPIO_P1_DIR_SET (0x070)
44#define LPC32XX_GPIO_P1_DIR_CLR (0x074)
45#define LPC32XX_GPIO_P1_DIR_STATE (0x078)
21
46
22#define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000)
23#define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004)
24#define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008)
25#define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C)
26#define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010)
27#define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014)
28#define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018)
29#define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C)
30#define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020)
31#define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024)
32#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
33#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
34#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
35#define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040)
36#define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044)
37#define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048)
38#define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C)
39#define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050)
40#define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054)
41#define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058)
42#define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060)
43#define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064)
44#define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068)
45#define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C)
46#define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070)
47#define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074)
48#define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078)
49
50#define GPIO012_PIN_TO_BIT(x) (1 << (x))
51#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
52#define GPO3_PIN_TO_BIT(x) (1 << (x))
53#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
54#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
55#define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
56#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
57#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)

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67#define LPC32XX_GPIO_P0_GRP 0
68#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
69#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
70#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
71#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
72#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
73
74struct gpio_regs {
47#define GPIO012_PIN_TO_BIT(x) (1 << (x))
48#define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25))
49#define GPO3_PIN_TO_BIT(x) (1 << (x))
50#define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)
51#define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x))
52#define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1)
53#define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1)
54#define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1)

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64#define LPC32XX_GPIO_P0_GRP 0
65#define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX)
66#define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX)
67#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX)
68#define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX)
69#define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX)
70
71struct gpio_regs {
75 void __iomem *inp_state;
76 void __iomem *outp_state;
77 void __iomem *outp_set;
78 void __iomem *outp_clr;
79 void __iomem *dir_set;
80 void __iomem *dir_clr;
72 unsigned long inp_state;
73 unsigned long outp_state;
74 unsigned long outp_set;
75 unsigned long outp_clr;
76 unsigned long dir_set;
77 unsigned long dir_clr;
81};
82
83/*
84 * GPIO names
85 */
86static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
87 "p0.0", "p0.1", "p0.2", "p0.3",
88 "p0.4", "p0.5", "p0.6", "p0.7"

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160 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
161 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
162 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
163};
164
165struct lpc32xx_gpio_chip {
166 struct gpio_chip chip;
167 struct gpio_regs *gpio_grp;
78};
79
80/*
81 * GPIO names
82 */
83static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = {
84 "p0.0", "p0.1", "p0.2", "p0.3",
85 "p0.4", "p0.5", "p0.6", "p0.7"

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157 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR,
158 .dir_set = LPC32XX_GPIO_P2_DIR_SET,
159 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR,
160};
161
162struct lpc32xx_gpio_chip {
163 struct gpio_chip chip;
164 struct gpio_regs *gpio_grp;
165 void __iomem *reg_base;
168};
169
166};
167
168static inline u32 gpreg_read(struct lpc32xx_gpio_chip *group, unsigned long offset)
169{
170 return __raw_readl(group->reg_base + offset);
171}
172
173static inline void gpreg_write(struct lpc32xx_gpio_chip *group, u32 val, unsigned long offset)
174{
175 __raw_writel(val, group->reg_base + offset);
176}
177
170static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
171 unsigned pin, int input)
172{
173 if (input)
178static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group,
179 unsigned pin, int input)
180{
181 if (input)
174 __raw_writel(GPIO012_PIN_TO_BIT(pin),
182 gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
175 group->gpio_grp->dir_clr);
176 else
183 group->gpio_grp->dir_clr);
184 else
177 __raw_writel(GPIO012_PIN_TO_BIT(pin),
185 gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
178 group->gpio_grp->dir_set);
179}
180
181static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
182 unsigned pin, int input)
183{
184 u32 u = GPIO3_PIN_TO_BIT(pin);
185
186 if (input)
186 group->gpio_grp->dir_set);
187}
188
189static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group,
190 unsigned pin, int input)
191{
192 u32 u = GPIO3_PIN_TO_BIT(pin);
193
194 if (input)
187 __raw_writel(u, group->gpio_grp->dir_clr);
195 gpreg_write(group, u, group->gpio_grp->dir_clr);
188 else
196 else
189 __raw_writel(u, group->gpio_grp->dir_set);
197 gpreg_write(group, u, group->gpio_grp->dir_set);
190}
191
192static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
193 unsigned pin, int high)
194{
195 if (high)
198}
199
200static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group,
201 unsigned pin, int high)
202{
203 if (high)
196 __raw_writel(GPIO012_PIN_TO_BIT(pin),
204 gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
197 group->gpio_grp->outp_set);
198 else
205 group->gpio_grp->outp_set);
206 else
199 __raw_writel(GPIO012_PIN_TO_BIT(pin),
207 gpreg_write(group, GPIO012_PIN_TO_BIT(pin),
200 group->gpio_grp->outp_clr);
201}
202
203static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
204 unsigned pin, int high)
205{
206 u32 u = GPIO3_PIN_TO_BIT(pin);
207
208 if (high)
208 group->gpio_grp->outp_clr);
209}
210
211static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group,
212 unsigned pin, int high)
213{
214 u32 u = GPIO3_PIN_TO_BIT(pin);
215
216 if (high)
209 __raw_writel(u, group->gpio_grp->outp_set);
217 gpreg_write(group, u, group->gpio_grp->outp_set);
210 else
218 else
211 __raw_writel(u, group->gpio_grp->outp_clr);
219 gpreg_write(group, u, group->gpio_grp->outp_clr);
212}
213
214static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
215 unsigned pin, int high)
216{
217 if (high)
220}
221
222static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group,
223 unsigned pin, int high)
224{
225 if (high)
218 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
226 gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set);
219 else
227 else
220 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
228 gpreg_write(group, GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr);
221}
222
223static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
224 unsigned pin)
225{
229}
230
231static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group,
232 unsigned pin)
233{
226 return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state),
234 return GPIO012_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state),
227 pin);
228}
229
230static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
231 unsigned pin)
232{
235 pin);
236}
237
238static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group,
239 unsigned pin)
240{
233 int state = __raw_readl(group->gpio_grp->inp_state);
241 int state = gpreg_read(group, group->gpio_grp->inp_state);
234
235 /*
236 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
237 * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
238 */
239 return GPIO3_PIN_IN_SEL(state, pin);
240}
241
242static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
243 unsigned pin)
244{
242
243 /*
244 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped
245 * to bits 10..14, while GPIOP3-5 is mapped to bit 24.
246 */
247 return GPIO3_PIN_IN_SEL(state, pin);
248}
249
250static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group,
251 unsigned pin)
252{
245 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin);
253 return GPI3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->inp_state), pin);
246}
247
248static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
249 unsigned pin)
250{
254}
255
256static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group,
257 unsigned pin)
258{
251 return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin);
259 return GPO3_PIN_IN_SEL(gpreg_read(group, group->gpio_grp->outp_state), pin);
252}
253
254/*
255 * GPIO primitives.
256 */
257static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
258 unsigned pin)
259{

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492 if (flags)
493 *flags = gpiospec->args[2];
494 return gpiospec->args[1];
495}
496
497static int lpc32xx_gpio_probe(struct platform_device *pdev)
498{
499 int i;
260}
261
262/*
263 * GPIO primitives.
264 */
265static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip,
266 unsigned pin)
267{

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500 if (flags)
501 *flags = gpiospec->args[2];
502 return gpiospec->args[1];
503}
504
505static int lpc32xx_gpio_probe(struct platform_device *pdev)
506{
507 int i;
508 void __iomem *reg_base;
500
509
510 reg_base = devm_platform_ioremap_resource(pdev, 0);
511 if (IS_ERR(reg_base))
512 return PTR_ERR(reg_base);
513
501 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
502 if (pdev->dev.of_node) {
503 lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
504 lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
505 lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
514 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) {
515 if (pdev->dev.of_node) {
516 lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate;
517 lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3;
518 lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node;
519 lpc32xx_gpiochip[i].reg_base = reg_base;
506 }
507 devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
508 &lpc32xx_gpiochip[i]);
509 }
510
511 return 0;
512}
513

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522 .driver = {
523 .name = "lpc32xx-gpio",
524 .of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
525 },
526 .probe = lpc32xx_gpio_probe,
527};
528
529module_platform_driver(lpc32xx_gpio_driver);
520 }
521 devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip,
522 &lpc32xx_gpiochip[i]);
523 }
524
525 return 0;
526}
527

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536 .driver = {
537 .name = "lpc32xx-gpio",
538 .of_match_table = of_match_ptr(lpc32xx_gpio_of_match),
539 },
540 .probe = lpc32xx_gpio_probe,
541};
542
543module_platform_driver(lpc32xx_gpio_driver);
544
545MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
546MODULE_LICENSE("GPL");
547MODULE_DESCRIPTION("GPIO driver for LPC32xx SoC");