gpio-f7188x.c (470308d9d2e0fc4367870e58ccd5f2e182c71d92) gpio-f7188x.c (d0918a84aff0ad5036f8bb2e375c851c07381940)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * GPIO driver for Fintek Super-I/O F71869, F71869A, F71882, F71889 and F81866
3 * GPIO driver for Fintek and Nuvoton Super-I/O chips
4 *
5 * Copyright (C) 2010-2013 LaCie
6 *
7 * Author: Simon Guinot <simon.guinot@sequanux.org>
8 */
9
10#define DRVNAME "gpio-f7188x"
11#define pr_fmt(fmt) DRVNAME ": " fmt

--- 5 unchanged lines hidden (view full) ---

17#include <linux/gpio/driver.h>
18#include <linux/bitops.h>
19
20/*
21 * Super-I/O registers
22 */
23#define SIO_LDSEL 0x07 /* Logical device select */
24#define SIO_DEVID 0x20 /* Device ID (2 bytes) */
4 *
5 * Copyright (C) 2010-2013 LaCie
6 *
7 * Author: Simon Guinot <simon.guinot@sequanux.org>
8 */
9
10#define DRVNAME "gpio-f7188x"
11#define pr_fmt(fmt) DRVNAME ": " fmt

--- 5 unchanged lines hidden (view full) ---

17#include <linux/gpio/driver.h>
18#include <linux/bitops.h>
19
20/*
21 * Super-I/O registers
22 */
23#define SIO_LDSEL 0x07 /* Logical device select */
24#define SIO_DEVID 0x20 /* Device ID (2 bytes) */
25#define SIO_DEVREV 0x22 /* Device revision */
26#define SIO_MANID 0x23 /* Fintek ID (2 bytes) */
27
25
28#define SIO_LD_GPIO 0x06 /* GPIO logical device */
29#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
30#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
31
26#define SIO_UNLOCK_KEY 0x87 /* Key to enable Super-I/O */
27#define SIO_LOCK_KEY 0xAA /* Key to disable Super-I/O */
28
32#define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
29/*
30 * Fintek devices.
31 */
32#define SIO_FINTEK_DEVREV 0x22 /* Fintek Device revision */
33#define SIO_FINTEK_MANID 0x23 /* Fintek ID (2 bytes) */
34
35#define SIO_FINTEK_ID 0x1934 /* Manufacturer ID */
36
33#define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
34#define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
35#define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
36#define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
37#define SIO_F71889A_ID 0x1005 /* F71889A chipset ID */
38#define SIO_F81866_ID 0x1010 /* F81866 chipset ID */
37#define SIO_F71869_ID 0x0814 /* F71869 chipset ID */
38#define SIO_F71869A_ID 0x1007 /* F71869A chipset ID */
39#define SIO_F71882_ID 0x0541 /* F71882 chipset ID */
40#define SIO_F71889_ID 0x0909 /* F71889 chipset ID */
41#define SIO_F71889A_ID 0x1005 /* F71889A chipset ID */
42#define SIO_F81866_ID 0x1010 /* F81866 chipset ID */
39#define SIO_F81804_ID 0x1502 /* F81804 chipset ID, same for f81966 */
43#define SIO_F81804_ID 0x1502 /* F81804 chipset ID, same for F81966 */
40#define SIO_F81865_ID 0x0704 /* F81865 chipset ID */
41
44#define SIO_F81865_ID 0x0704 /* F81865 chipset ID */
45
46#define SIO_LD_GPIO_FINTEK 0x06 /* GPIO logical device */
42
47
48/*
49 * Nuvoton devices.
50 */
51#define SIO_NCT6116D_ID 0xD283 /* NCT6116D chipset ID */
52
53#define SIO_LD_GPIO_NUVOTON 0x07 /* GPIO logical device */
54
55
43enum chips {
44 f71869,
45 f71869a,
46 f71882fg,
47 f71889a,
48 f71889f,
49 f81866,
50 f81804,
51 f81865,
56enum chips {
57 f71869,
58 f71869a,
59 f71882fg,
60 f71889a,
61 f71889f,
62 f81866,
63 f81804,
64 f81865,
65 nct6116d,
52};
53
54static const char * const f7188x_names[] = {
55 "f71869",
56 "f71869a",
57 "f71882fg",
58 "f71889a",
59 "f71889f",
60 "f81866",
61 "f81804",
62 "f81865",
66};
67
68static const char * const f7188x_names[] = {
69 "f71869",
70 "f71869a",
71 "f71882fg",
72 "f71889a",
73 "f71889f",
74 "f81866",
75 "f81804",
76 "f81865",
77 "nct6116d",
63};
64
65struct f7188x_sio {
66 int addr;
78};
79
80struct f7188x_sio {
81 int addr;
82 int device;
67 enum chips type;
68};
69
70struct f7188x_gpio_bank {
71 struct gpio_chip chip;
72 unsigned int regbase;
73 struct f7188x_gpio_data *data;
74};

--- 91 unchanged lines hidden (view full) ---

166 }
167
168#define f7188x_gpio_dir(base) ((base) + 0)
169#define f7188x_gpio_data_out(base) ((base) + 1)
170#define f7188x_gpio_data_in(base) ((base) + 2)
171/* Output mode register (0:open drain 1:push-pull). */
172#define f7188x_gpio_out_mode(base) ((base) + 3)
173
83 enum chips type;
84};
85
86struct f7188x_gpio_bank {
87 struct gpio_chip chip;
88 unsigned int regbase;
89 struct f7188x_gpio_data *data;
90};

--- 91 unchanged lines hidden (view full) ---

182 }
183
184#define f7188x_gpio_dir(base) ((base) + 0)
185#define f7188x_gpio_data_out(base) ((base) + 1)
186#define f7188x_gpio_data_in(base) ((base) + 2)
187/* Output mode register (0:open drain 1:push-pull). */
188#define f7188x_gpio_out_mode(base) ((base) + 3)
189
190#define f7188x_gpio_dir_invert(type) ((type) == nct6116d)
191#define f7188x_gpio_data_single(type) ((type) == nct6116d)
192
174static struct f7188x_gpio_bank f71869_gpio_bank[] = {
175 F7188X_GPIO_BANK(0, 6, 0xF0),
176 F7188X_GPIO_BANK(10, 8, 0xE0),
177 F7188X_GPIO_BANK(20, 8, 0xD0),
178 F7188X_GPIO_BANK(30, 8, 0xC0),
179 F7188X_GPIO_BANK(40, 8, 0xB0),
180 F7188X_GPIO_BANK(50, 5, 0xA0),
181 F7188X_GPIO_BANK(60, 6, 0x90),

--- 68 unchanged lines hidden (view full) ---

250 F7188X_GPIO_BANK(10, 8, 0xE0),
251 F7188X_GPIO_BANK(20, 8, 0xD0),
252 F7188X_GPIO_BANK(30, 8, 0xC0),
253 F7188X_GPIO_BANK(40, 8, 0xB0),
254 F7188X_GPIO_BANK(50, 8, 0xA0),
255 F7188X_GPIO_BANK(60, 5, 0x90),
256};
257
193static struct f7188x_gpio_bank f71869_gpio_bank[] = {
194 F7188X_GPIO_BANK(0, 6, 0xF0),
195 F7188X_GPIO_BANK(10, 8, 0xE0),
196 F7188X_GPIO_BANK(20, 8, 0xD0),
197 F7188X_GPIO_BANK(30, 8, 0xC0),
198 F7188X_GPIO_BANK(40, 8, 0xB0),
199 F7188X_GPIO_BANK(50, 5, 0xA0),
200 F7188X_GPIO_BANK(60, 6, 0x90),

--- 68 unchanged lines hidden (view full) ---

269 F7188X_GPIO_BANK(10, 8, 0xE0),
270 F7188X_GPIO_BANK(20, 8, 0xD0),
271 F7188X_GPIO_BANK(30, 8, 0xC0),
272 F7188X_GPIO_BANK(40, 8, 0xB0),
273 F7188X_GPIO_BANK(50, 8, 0xA0),
274 F7188X_GPIO_BANK(60, 5, 0x90),
275};
276
277static struct f7188x_gpio_bank nct6116d_gpio_bank[] = {
278 F7188X_GPIO_BANK(0, 8, 0xE0),
279 F7188X_GPIO_BANK(10, 8, 0xE4),
280 F7188X_GPIO_BANK(20, 8, 0xE8),
281 F7188X_GPIO_BANK(30, 8, 0xEC),
282 F7188X_GPIO_BANK(40, 8, 0xF0),
283 F7188X_GPIO_BANK(50, 8, 0xF4),
284 F7188X_GPIO_BANK(60, 8, 0xF8),
285 F7188X_GPIO_BANK(70, 1, 0xFC),
286};
287
258static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
259{
260 int err;
261 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
262 struct f7188x_sio *sio = bank->data->sio;
263 u8 dir;
264
265 err = superio_enter(sio->addr);
266 if (err)
267 return err;
288static int f7188x_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
289{
290 int err;
291 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
292 struct f7188x_sio *sio = bank->data->sio;
293 u8 dir;
294
295 err = superio_enter(sio->addr);
296 if (err)
297 return err;
268 superio_select(sio->addr, SIO_LD_GPIO);
298 superio_select(sio->addr, sio->device);
269
270 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
271
272 superio_exit(sio->addr);
273
299
300 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
301
302 superio_exit(sio->addr);
303
274 if (dir & 1 << offset)
304 if (f7188x_gpio_dir_invert(sio->type))
305 dir = ~dir;
306
307 if (dir & BIT(offset))
275 return GPIO_LINE_DIRECTION_OUT;
276
277 return GPIO_LINE_DIRECTION_IN;
278}
279
280static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
281{
282 int err;
283 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
284 struct f7188x_sio *sio = bank->data->sio;
285 u8 dir;
286
287 err = superio_enter(sio->addr);
288 if (err)
289 return err;
308 return GPIO_LINE_DIRECTION_OUT;
309
310 return GPIO_LINE_DIRECTION_IN;
311}
312
313static int f7188x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
314{
315 int err;
316 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
317 struct f7188x_sio *sio = bank->data->sio;
318 u8 dir;
319
320 err = superio_enter(sio->addr);
321 if (err)
322 return err;
290 superio_select(sio->addr, SIO_LD_GPIO);
323 superio_select(sio->addr, sio->device);
291
292 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
324
325 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
293 dir &= ~BIT(offset);
326
327 if (f7188x_gpio_dir_invert(sio->type))
328 dir |= BIT(offset);
329 else
330 dir &= ~BIT(offset);
294 superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir);
295
296 superio_exit(sio->addr);
297
298 return 0;
299}
300
301static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
302{
303 int err;
304 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
305 struct f7188x_sio *sio = bank->data->sio;
306 u8 dir, data;
307
308 err = superio_enter(sio->addr);
309 if (err)
310 return err;
331 superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir);
332
333 superio_exit(sio->addr);
334
335 return 0;
336}
337
338static int f7188x_gpio_get(struct gpio_chip *chip, unsigned offset)
339{
340 int err;
341 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
342 struct f7188x_sio *sio = bank->data->sio;
343 u8 dir, data;
344
345 err = superio_enter(sio->addr);
346 if (err)
347 return err;
311 superio_select(sio->addr, SIO_LD_GPIO);
348 superio_select(sio->addr, sio->device);
312
313 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
314 dir = !!(dir & BIT(offset));
349
350 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
351 dir = !!(dir & BIT(offset));
315 if (dir)
352 if (f7188x_gpio_data_single(sio->type) || dir)
316 data = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));
317 else
318 data = superio_inb(sio->addr, f7188x_gpio_data_in(bank->regbase));
319
320 superio_exit(sio->addr);
321
322 return !!(data & BIT(offset));
323}

--- 4 unchanged lines hidden (view full) ---

328 int err;
329 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
330 struct f7188x_sio *sio = bank->data->sio;
331 u8 dir, data_out;
332
333 err = superio_enter(sio->addr);
334 if (err)
335 return err;
353 data = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));
354 else
355 data = superio_inb(sio->addr, f7188x_gpio_data_in(bank->regbase));
356
357 superio_exit(sio->addr);
358
359 return !!(data & BIT(offset));
360}

--- 4 unchanged lines hidden (view full) ---

365 int err;
366 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
367 struct f7188x_sio *sio = bank->data->sio;
368 u8 dir, data_out;
369
370 err = superio_enter(sio->addr);
371 if (err)
372 return err;
336 superio_select(sio->addr, SIO_LD_GPIO);
373 superio_select(sio->addr, sio->device);
337
338 data_out = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));
339 if (value)
340 data_out |= BIT(offset);
341 else
342 data_out &= ~BIT(offset);
343 superio_outb(sio->addr, f7188x_gpio_data_out(bank->regbase), data_out);
344
345 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
374
375 data_out = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));
376 if (value)
377 data_out |= BIT(offset);
378 else
379 data_out &= ~BIT(offset);
380 superio_outb(sio->addr, f7188x_gpio_data_out(bank->regbase), data_out);
381
382 dir = superio_inb(sio->addr, f7188x_gpio_dir(bank->regbase));
346 dir |= BIT(offset);
383 if (f7188x_gpio_dir_invert(sio->type))
384 dir &= ~BIT(offset);
385 else
386 dir |= BIT(offset);
347 superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir);
348
349 superio_exit(sio->addr);
350
351 return 0;
352}
353
354static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
355{
356 int err;
357 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
358 struct f7188x_sio *sio = bank->data->sio;
359 u8 data_out;
360
361 err = superio_enter(sio->addr);
362 if (err)
363 return;
387 superio_outb(sio->addr, f7188x_gpio_dir(bank->regbase), dir);
388
389 superio_exit(sio->addr);
390
391 return 0;
392}
393
394static void f7188x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
395{
396 int err;
397 struct f7188x_gpio_bank *bank = gpiochip_get_data(chip);
398 struct f7188x_sio *sio = bank->data->sio;
399 u8 data_out;
400
401 err = superio_enter(sio->addr);
402 if (err)
403 return;
364 superio_select(sio->addr, SIO_LD_GPIO);
404 superio_select(sio->addr, sio->device);
365
366 data_out = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));
367 if (value)
368 data_out |= BIT(offset);
369 else
370 data_out &= ~BIT(offset);
371 superio_outb(sio->addr, f7188x_gpio_data_out(bank->regbase), data_out);
372

--- 11 unchanged lines hidden (view full) ---

384
385 if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN &&
386 param != PIN_CONFIG_DRIVE_PUSH_PULL)
387 return -ENOTSUPP;
388
389 err = superio_enter(sio->addr);
390 if (err)
391 return err;
405
406 data_out = superio_inb(sio->addr, f7188x_gpio_data_out(bank->regbase));
407 if (value)
408 data_out |= BIT(offset);
409 else
410 data_out &= ~BIT(offset);
411 superio_outb(sio->addr, f7188x_gpio_data_out(bank->regbase), data_out);
412

--- 11 unchanged lines hidden (view full) ---

424
425 if (param != PIN_CONFIG_DRIVE_OPEN_DRAIN &&
426 param != PIN_CONFIG_DRIVE_PUSH_PULL)
427 return -ENOTSUPP;
428
429 err = superio_enter(sio->addr);
430 if (err)
431 return err;
392 superio_select(sio->addr, SIO_LD_GPIO);
432 superio_select(sio->addr, sio->device);
393
394 data = superio_inb(sio->addr, f7188x_gpio_out_mode(bank->regbase));
395 if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN)
396 data &= ~BIT(offset);
397 else
398 data |= BIT(offset);
399 superio_outb(sio->addr, f7188x_gpio_out_mode(bank->regbase), data);
400

--- 44 unchanged lines hidden (view full) ---

445 case f81804:
446 data->nr_bank = ARRAY_SIZE(f81804_gpio_bank);
447 data->bank = f81804_gpio_bank;
448 break;
449 case f81865:
450 data->nr_bank = ARRAY_SIZE(f81865_gpio_bank);
451 data->bank = f81865_gpio_bank;
452 break;
433
434 data = superio_inb(sio->addr, f7188x_gpio_out_mode(bank->regbase));
435 if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN)
436 data &= ~BIT(offset);
437 else
438 data |= BIT(offset);
439 superio_outb(sio->addr, f7188x_gpio_out_mode(bank->regbase), data);
440

--- 44 unchanged lines hidden (view full) ---

485 case f81804:
486 data->nr_bank = ARRAY_SIZE(f81804_gpio_bank);
487 data->bank = f81804_gpio_bank;
488 break;
489 case f81865:
490 data->nr_bank = ARRAY_SIZE(f81865_gpio_bank);
491 data->bank = f81865_gpio_bank;
492 break;
493 case nct6116d:
494 data->nr_bank = ARRAY_SIZE(nct6116d_gpio_bank);
495 data->bank = nct6116d_gpio_bank;
496 break;
453 default:
454 return -ENODEV;
455 }
456 data->sio = sio;
457
458 platform_set_drvdata(pdev, data);
459
460 /* For each GPIO bank, register a GPIO chip. */

--- 14 unchanged lines hidden (view full) ---

475
476 return 0;
477}
478
479static int __init f7188x_find(int addr, struct f7188x_sio *sio)
480{
481 int err;
482 u16 devid;
497 default:
498 return -ENODEV;
499 }
500 data->sio = sio;
501
502 platform_set_drvdata(pdev, data);
503
504 /* For each GPIO bank, register a GPIO chip. */

--- 14 unchanged lines hidden (view full) ---

519
520 return 0;
521}
522
523static int __init f7188x_find(int addr, struct f7188x_sio *sio)
524{
525 int err;
526 u16 devid;
527 u16 manid;
483
484 err = superio_enter(addr);
485 if (err)
486 return err;
487
488 err = -ENODEV;
528
529 err = superio_enter(addr);
530 if (err)
531 return err;
532
533 err = -ENODEV;
489 devid = superio_inw(addr, SIO_MANID);
490 if (devid != SIO_FINTEK_ID) {
491 pr_debug("Not a Fintek device at 0x%08x\n", addr);
492 goto err;
493 }
494
534
535 sio->device = SIO_LD_GPIO_FINTEK;
495 devid = superio_inw(addr, SIO_DEVID);
496 switch (devid) {
497 case SIO_F71869_ID:
498 sio->type = f71869;
499 break;
500 case SIO_F71869A_ID:
501 sio->type = f71869a;
502 break;

--- 10 unchanged lines hidden (view full) ---

513 sio->type = f81866;
514 break;
515 case SIO_F81804_ID:
516 sio->type = f81804;
517 break;
518 case SIO_F81865_ID:
519 sio->type = f81865;
520 break;
536 devid = superio_inw(addr, SIO_DEVID);
537 switch (devid) {
538 case SIO_F71869_ID:
539 sio->type = f71869;
540 break;
541 case SIO_F71869A_ID:
542 sio->type = f71869a;
543 break;

--- 10 unchanged lines hidden (view full) ---

554 sio->type = f81866;
555 break;
556 case SIO_F81804_ID:
557 sio->type = f81804;
558 break;
559 case SIO_F81865_ID:
560 sio->type = f81865;
561 break;
562 case SIO_NCT6116D_ID:
563 sio->device = SIO_LD_GPIO_NUVOTON;
564 sio->type = nct6116d;
565 break;
521 default:
522 pr_info("Unsupported Fintek device 0x%04x\n", devid);
523 goto err;
524 }
566 default:
567 pr_info("Unsupported Fintek device 0x%04x\n", devid);
568 goto err;
569 }
570
571 /* double check manufacturer where possible */
572 if (sio->type != nct6116d) {
573 manid = superio_inw(addr, SIO_FINTEK_MANID);
574 if (manid != SIO_FINTEK_ID) {
575 pr_debug("Not a Fintek device at 0x%08x\n", addr);
576 goto err;
577 }
578 }
579
525 sio->addr = addr;
526 err = 0;
527
580 sio->addr = addr;
581 err = 0;
582
528 pr_info("Found %s at %#x, revision %d\n",
529 f7188x_names[sio->type],
530 (unsigned int) addr,
531 (int) superio_inb(addr, SIO_DEVREV));
583 pr_info("Found %s at %#x\n", f7188x_names[sio->type], (unsigned int)addr);
584 if (sio->type != nct6116d)
585 pr_info(" revision %d\n", superio_inb(addr, SIO_FINTEK_DEVREV));
532
533err:
534 superio_exit(addr);
535 return err;
536}
537
538static struct platform_device *f7188x_gpio_pdev;
539

--- 73 unchanged lines hidden --- 		586
587err:
588 superio_exit(addr);
589 return err;
590}
591
592static struct platform_device *f7188x_gpio_pdev;
593

--- 73 unchanged lines hidden ---