dfl-fme-mgr.c (e42f6f9be4f83c537aa81b4c6239ea94ff5b29ce) dfl-fme-mgr.c (83b15fed91fa23facd159fb72c82241cbdc93d3f)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * FPGA Manager Driver for FPGA Management Engine (FME)
4 *
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
6 *
7 * Authors:
8 * Kang Luwei <luwei.kang@intel.com>

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196 }
197 udelay(1);
198
199 pr_status = readq(fme_pr + FME_PR_STS);
200 pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
201 }
202
203 if (count < 4) {
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * FPGA Manager Driver for FPGA Management Engine (FME)
4 *
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
6 *
7 * Authors:
8 * Kang Luwei <luwei.kang@intel.com>

--- 187 unchanged lines hidden (view full) ---

196 }
197 udelay(1);
198
199 pr_status = readq(fme_pr + FME_PR_STS);
200 pr_credit = FIELD_GET(FME_PR_STS_PR_CREDIT, pr_status);
201 }
202
203 if (count < 4) {
204 dev_err(dev, "Invaild PR bitstream size\n");
204 dev_err(dev, "Invalid PR bitstream size\n");
205 return -EINVAL;
206 }
207
208 pr_data = 0;
209 pr_data |= FIELD_PREP(FME_PR_DATA_PR_DATA_RAW,
210 *(((u32 *)buf) + i));
211 writeq(pr_data, fme_pr + FME_PR_DATA);
212 count -= 4;

--- 137 unchanged lines hidden --- 		205 return -EINVAL;
206 }
207
208 pr_data = 0;
209 pr_data |= FIELD_PREP(FME_PR_DATA_PR_DATA_RAW,
210 *(((u32 *)buf) + i));
211 writeq(pr_data, fme_pr + FME_PR_DATA);
212 count -= 4;

--- 137 unchanged lines hidden ---