dfl-fme-mgr.c (af275ec6160ba68714371cfe0575f9aa478ce02f) dfl-fme-mgr.c (5ebae801d960d46e39574cb83ec24ab44d1a6c2a)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * FPGA Manager Driver for FPGA Management Engine (FME)
4 *
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
6 *
7 * Authors:
8 * Kang Luwei <luwei.kang@intel.com>

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267static const struct fpga_manager_ops fme_mgr_ops = {
268 .write_init = fme_mgr_write_init,
269 .write = fme_mgr_write,
270 .write_complete = fme_mgr_write_complete,
271 .state = fme_mgr_state,
272 .status = fme_mgr_status,
273};
274
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * FPGA Manager Driver for FPGA Management Engine (FME)
4 *
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
6 *
7 * Authors:
8 * Kang Luwei <luwei.kang@intel.com>

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267static const struct fpga_manager_ops fme_mgr_ops = {
268 .write_init = fme_mgr_write_init,
269 .write = fme_mgr_write,
270 .write_complete = fme_mgr_write_complete,
271 .state = fme_mgr_state,
272 .status = fme_mgr_status,
273};
274
275static void fme_mgr_get_compat_id(void __iomem *fme_pr,
276 struct fpga_compat_id *id)
277{
278 id->id_l = readq(fme_pr + FME_PR_INTFC_ID_L);
279 id->id_h = readq(fme_pr + FME_PR_INTFC_ID_H);
280}
281
275static int fme_mgr_probe(struct platform_device *pdev)
276{
277 struct dfl_fme_mgr_pdata *pdata = dev_get_platdata(&pdev->dev);
282static int fme_mgr_probe(struct platform_device *pdev)
283{
284 struct dfl_fme_mgr_pdata *pdata = dev_get_platdata(&pdev->dev);
285 struct fpga_compat_id *compat_id;
278 struct device *dev = &pdev->dev;
279 struct fme_mgr_priv *priv;
280 struct fpga_manager *mgr;
281 struct resource *res;
282 int ret;
283
284 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
285 if (!priv)

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290
291 if (!priv->ioaddr) {
292 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
293 priv->ioaddr = devm_ioremap_resource(dev, res);
294 if (IS_ERR(priv->ioaddr))
295 return PTR_ERR(priv->ioaddr);
296 }
297
286 struct device *dev = &pdev->dev;
287 struct fme_mgr_priv *priv;
288 struct fpga_manager *mgr;
289 struct resource *res;
290 int ret;
291
292 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
293 if (!priv)

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298
299 if (!priv->ioaddr) {
300 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
301 priv->ioaddr = devm_ioremap_resource(dev, res);
302 if (IS_ERR(priv->ioaddr))
303 return PTR_ERR(priv->ioaddr);
304 }
305
306 compat_id = devm_kzalloc(dev, sizeof(*compat_id), GFP_KERNEL);
307 if (!compat_id)
308 return -ENOMEM;
309
310 fme_mgr_get_compat_id(priv->ioaddr, compat_id);
311
298 mgr = fpga_mgr_create(dev, "DFL FME FPGA Manager",
299 &fme_mgr_ops, priv);
300 if (!mgr)
301 return -ENOMEM;
302
312 mgr = fpga_mgr_create(dev, "DFL FME FPGA Manager",
313 &fme_mgr_ops, priv);
314 if (!mgr)
315 return -ENOMEM;
316
317 mgr->compat_id = compat_id;
303 platform_set_drvdata(pdev, mgr);
304
305 ret = fpga_mgr_register(mgr);
306 if (ret)
307 fpga_mgr_free(mgr);
308
309 return ret;
310}

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318 platform_set_drvdata(pdev, mgr);
319
320 ret = fpga_mgr_register(mgr);
321 if (ret)
322 fpga_mgr_free(mgr);
323
324 return ret;
325}

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