dfl-fme-mgr.c (3eb66e91a25497065c5322b1268cbc3953642227) dfl-fme-mgr.c (e150e3f4ad9aeda7610dee09f98ea69e0bc701b7)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * FPGA Manager Driver for FPGA Management Engine (FME)
4 *
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
6 *
7 * Authors:
8 * Kang Luwei <luwei.kang@intel.com>

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25#include "dfl-fme-pr.h"
26
27/* FME Partial Reconfiguration Sub Feature Register Set */
28#define FME_PR_DFH 0x0
29#define FME_PR_CTRL 0x8
30#define FME_PR_STS 0x10
31#define FME_PR_DATA 0x18
32#define FME_PR_ERR 0x20
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * FPGA Manager Driver for FPGA Management Engine (FME)
4 *
5 * Copyright (C) 2017-2018 Intel Corporation, Inc.
6 *
7 * Authors:
8 * Kang Luwei <luwei.kang@intel.com>

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25#include "dfl-fme-pr.h"
26
27/* FME Partial Reconfiguration Sub Feature Register Set */
28#define FME_PR_DFH 0x0
29#define FME_PR_CTRL 0x8
30#define FME_PR_STS 0x10
31#define FME_PR_DATA 0x18
32#define FME_PR_ERR 0x20
33#define FME_PR_INTFC_ID_H 0xA8
34#define FME_PR_INTFC_ID_L 0xB0
33#define FME_PR_INTFC_ID_L 0xA8
34#define FME_PR_INTFC_ID_H 0xB0
35
36/* FME PR Control Register Bitfield */
37#define FME_PR_CTRL_PR_RST BIT_ULL(0) /* Reset PR engine */
38#define FME_PR_CTRL_PR_RSTACK BIT_ULL(4) /* Ack for PR engine reset */
39#define FME_PR_CTRL_PR_RGN_ID GENMASK_ULL(9, 7) /* PR Region ID */
40#define FME_PR_CTRL_PR_START BIT_ULL(12) /* Start to request PR service */
41#define FME_PR_CTRL_PR_COMPLETE BIT_ULL(13) /* PR data push completion */
42

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35
36/* FME PR Control Register Bitfield */
37#define FME_PR_CTRL_PR_RST BIT_ULL(0) /* Reset PR engine */
38#define FME_PR_CTRL_PR_RSTACK BIT_ULL(4) /* Ack for PR engine reset */
39#define FME_PR_CTRL_PR_RGN_ID GENMASK_ULL(9, 7) /* PR Region ID */
40#define FME_PR_CTRL_PR_START BIT_ULL(12) /* Start to request PR service */
41#define FME_PR_CTRL_PR_COMPLETE BIT_ULL(13) /* PR data push completion */
42

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