| zynqmp.c (fc9fb8fb985c092f9cf01c7c50269c132efc4d58) | zynqmp.c (0667a8d144bc830d0a752f079c9789735cd4f1f8) |
|---|---|
| 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Xilinx Zynq MPSoC Firmware layer 4 * 5 * Copyright (C) 2014-2018 Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 * Davorin Mista <davorin.mista@aggios.com> --- 408 unchanged lines hidden (view full) --- 417 * @clock_id: ID of the clock 418 * @divider: divider value 419 * 420 * This function is used by master to get divider values 421 * for any clock. 422 * 423 * Return: Returns status, either success or error+reason 424 */ | 1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Xilinx Zynq MPSoC Firmware layer 4 * 5 * Copyright (C) 2014-2018 Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 * Davorin Mista <davorin.mista@aggios.com> --- 408 unchanged lines hidden (view full) --- 417 * @clock_id: ID of the clock 418 * @divider: divider value 419 * 420 * This function is used by master to get divider values 421 * for any clock. 422 * 423 * Return: Returns status, either success or error+reason 424 */ |
| 425static int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) | 425int zynqmp_pm_clock_getdivider(u32 clock_id, u32 *divider) |
| 426{ 427 u32 ret_payload[PAYLOAD_ARG_CNT]; 428 int ret; 429 430 ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETDIVIDER, clock_id, 0, 431 0, 0, ret_payload); 432 *divider = ret_payload[1]; 433 434 return ret; 435} | 426{ 427 u32 ret_payload[PAYLOAD_ARG_CNT]; 428 int ret; 429 430 ret = zynqmp_pm_invoke_fn(PM_CLOCK_GETDIVIDER, clock_id, 0, 431 0, 0, ret_payload); 432 *divider = ret_payload[1]; 433 434 return ret; 435} |
| 436EXPORT_SYMBOL_GPL(zynqmp_pm_clock_getdivider); |
|
| 436 437/** 438 * zynqmp_pm_clock_setrate() - Set the clock rate for given id 439 * @clock_id: ID of the clock 440 * @rate: rate value in hz 441 * 442 * This function is used by master to set rate for any clock. 443 * --- 292 unchanged lines hidden (view full) --- 736 lower_32_bits(address), 737 0, 0, ret_payload); 738 *out = ret_payload[1]; 739 740 return ret; 741} 742 743static const struct zynqmp_eemi_ops eemi_ops = { | 437 438/** 439 * zynqmp_pm_clock_setrate() - Set the clock rate for given id 440 * @clock_id: ID of the clock 441 * @rate: rate value in hz 442 * 443 * This function is used by master to set rate for any clock. 444 * --- 292 unchanged lines hidden (view full) --- 737 lower_32_bits(address), 738 0, 0, ret_payload); 739 *out = ret_payload[1]; 740 741 return ret; 742} 743 744static const struct zynqmp_eemi_ops eemi_ops = { |
| 744 .clock_getdivider = zynqmp_pm_clock_getdivider, | |
| 745 .clock_setrate = zynqmp_pm_clock_setrate, 746 .clock_getrate = zynqmp_pm_clock_getrate, 747 .clock_setparent = zynqmp_pm_clock_setparent, 748 .clock_getparent = zynqmp_pm_clock_getparent, 749 .ioctl = zynqmp_pm_ioctl, 750 .reset_assert = zynqmp_pm_reset_assert, 751 .reset_get_status = zynqmp_pm_reset_get_status, 752 .init_finalize = zynqmp_pm_init_finalize, --- 109 unchanged lines hidden --- | 745 .clock_setrate = zynqmp_pm_clock_setrate, 746 .clock_getrate = zynqmp_pm_clock_getrate, 747 .clock_setparent = zynqmp_pm_clock_setparent, 748 .clock_getparent = zynqmp_pm_clock_getparent, 749 .ioctl = zynqmp_pm_ioctl, 750 .reset_assert = zynqmp_pm_reset_assert, 751 .reset_get_status = zynqmp_pm_reset_get_status, 752 .init_finalize = zynqmp_pm_init_finalize, --- 109 unchanged lines hidden --- |