synopsys_edac.c (e926ae573b0f550de2b23883a1571cfa7ad7dff0) synopsys_edac.c (b500b4a029d577c6b5f3d7480ef2635dd1f30a55)
1/*
2 * Synopsys DDR ECC Driver
3 * This driver is based on ppc4xx_edac.c drivers
4 *
5 * Copyright (C) 2012 - 2014 Xilinx, Inc.
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by

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17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details
20 */
21
22#include <linux/edac.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
1/*
2 * Synopsys DDR ECC Driver
3 * This driver is based on ppc4xx_edac.c drivers
4 *
5 * Copyright (C) 2012 - 2014 Xilinx, Inc.
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by

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17 * This file is subject to the terms and conditions of the GNU General Public
18 * License. See the file "COPYING" in the main directory of this archive
19 * for more details
20 */
21
22#include <linux/edac.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/interrupt.h>
25#include <linux/of.h>
26#include <linux/of_device.h>
27
28#include "edac_module.h"
29
30/* Number of cs_rows needed per memory controller */
31#define SYNPS_EDAC_NR_CSROWS 1
32

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267
268/**
269 * struct ecc_error_info - ECC error log information.
270 * @row: Row number.
271 * @col: Column number.
272 * @bank: Bank number.
273 * @bitpos: Bit position.
274 * @data: Data causing the error.
26#include <linux/of.h>
27#include <linux/of_device.h>
28
29#include "edac_module.h"
30
31/* Number of cs_rows needed per memory controller */
32#define SYNPS_EDAC_NR_CSROWS 1
33

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268
269/**
270 * struct ecc_error_info - ECC error log information.
271 * @row: Row number.
272 * @col: Column number.
273 * @bank: Bank number.
274 * @bitpos: Bit position.
275 * @data: Data causing the error.
276 * @bankgrpnr: Bank group number.
277 * @blknr: Block number.
275 */
276struct ecc_error_info {
277 u32 row;
278 u32 col;
279 u32 bank;
280 u32 bitpos;
281 u32 data;
278 */
279struct ecc_error_info {
280 u32 row;
281 u32 col;
282 u32 bank;
283 u32 bitpos;
284 u32 data;
285 u32 bankgrpnr;
286 u32 blknr;
282};
283
284/**
285 * struct synps_ecc_status - ECC status information to report.
286 * @ce_cnt: Correctable error count.
287 * @ue_cnt: Uncorrectable error count.
288 * @ceinfo: Correctable error log information.
289 * @ueinfo: Uncorrectable error log information.

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380out:
381 writel(clearval, base + ECC_CTRL_OFST);
382 writel(0x0, base + ECC_CTRL_OFST);
383
384 return 0;
385}
386
387/**
287};
288
289/**
290 * struct synps_ecc_status - ECC status information to report.
291 * @ce_cnt: Correctable error count.
292 * @ue_cnt: Uncorrectable error count.
293 * @ceinfo: Correctable error log information.
294 * @ueinfo: Uncorrectable error log information.

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385out:
386 writel(clearval, base + ECC_CTRL_OFST);
387 writel(0x0, base + ECC_CTRL_OFST);
388
389 return 0;
390}
391
392/**
393 * zynqmp_get_error_info - Get the current ECC error info.
394 * @priv: DDR memory controller private instance data.
395 *
396 * Return: one if there is no error otherwise returns zero.
397 */
398static int zynqmp_get_error_info(struct synps_edac_priv *priv)
399{
400 struct synps_ecc_status *p;
401 u32 regval, clearval = 0;
402 void __iomem *base;
403
404 base = priv->baseaddr;
405 p = &priv->stat;
406
407 regval = readl(base + ECC_STAT_OFST);
408 if (!regval)
409 return 1;
410
411 p->ce_cnt = (regval & ECC_STAT_CECNT_MASK) >> ECC_STAT_CECNT_SHIFT;
412 p->ue_cnt = (regval & ECC_STAT_UECNT_MASK) >> ECC_STAT_UECNT_SHIFT;
413 if (!p->ce_cnt)
414 goto ue_err;
415
416 p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK);
417
418 regval = readl(base + ECC_CEADDR0_OFST);
419 p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK);
420 regval = readl(base + ECC_CEADDR1_OFST);
421 p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
422 ECC_CEADDR1_BNKNR_SHIFT;
423 p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
424 ECC_CEADDR1_BNKGRP_SHIFT;
425 p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
426 p->ceinfo.data = readl(base + ECC_CSYND0_OFST);
427 edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n",
428 readl(base + ECC_CSYND0_OFST), readl(base + ECC_CSYND1_OFST),
429 readl(base + ECC_CSYND2_OFST));
430ue_err:
431 if (!p->ue_cnt)
432 goto out;
433
434 regval = readl(base + ECC_UEADDR0_OFST);
435 p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK);
436 regval = readl(base + ECC_UEADDR1_OFST);
437 p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >>
438 ECC_CEADDR1_BNKGRP_SHIFT;
439 p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >>
440 ECC_CEADDR1_BNKNR_SHIFT;
441 p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK);
442 p->ueinfo.data = readl(base + ECC_UESYND0_OFST);
443out:
444 clearval = ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT;
445 clearval |= ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT;
446 writel(clearval, base + ECC_CLR_OFST);
447 writel(0x0, base + ECC_CLR_OFST);
448
449 return 0;
450}
451
452/**
388 * handle_error - Handle Correctable and Uncorrectable errors.
389 * @mci: EDAC memory controller instance.
390 * @p: Synopsys ECC status structure.
391 *
392 * Handles ECC correctable and uncorrectable errors.
393 */
394static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
395{
396 struct synps_edac_priv *priv = mci->pvt_info;
397 struct ecc_error_info *pinf;
398
399 if (p->ce_cnt) {
400 pinf = &p->ceinfo;
453 * handle_error - Handle Correctable and Uncorrectable errors.
454 * @mci: EDAC memory controller instance.
455 * @p: Synopsys ECC status structure.
456 *
457 * Handles ECC correctable and uncorrectable errors.
458 */
459static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
460{
461 struct synps_edac_priv *priv = mci->pvt_info;
462 struct ecc_error_info *pinf;
463
464 if (p->ce_cnt) {
465 pinf = &p->ceinfo;
401 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
402 "DDR ECC error type :%s Row %d Bank %d Col %d ",
403 "CE", pinf->row, pinf->bank, pinf->col);
466 if (!priv->p_data->quirks) {
467 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
468 "DDR ECC error type:%s Row %d Bank %d Col %d ",
469 "CE", pinf->row, pinf->bank, pinf->col);
470 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
471 "Bit Position: %d Data: 0x%08x\n",
472 pinf->bitpos, pinf->data);
473 } else {
474 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
475 "DDR ECC error type:%s Row %d Bank %d Col %d ",
476 "CE", pinf->row, pinf->bank, pinf->col);
477 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
478 "BankGroup Number %d Block Number %d ",
479 pinf->bankgrpnr, pinf->blknr);
480 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
481 "Bit Position: %d Data: 0x%08x\n",
482 pinf->bitpos, pinf->data);
483 }
484
404 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
405 p->ce_cnt, 0, 0, 0, 0, 0, -1,
406 priv->message, "");
407 }
408
409 if (p->ue_cnt) {
410 pinf = &p->ueinfo;
485 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci,
486 p->ce_cnt, 0, 0, 0, 0, 0, -1,
487 priv->message, "");
488 }
489
490 if (p->ue_cnt) {
491 pinf = &p->ueinfo;
411 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
412 "DDR ECC error type :%s Row %d Bank %d Col %d ",
413 "UE", pinf->row, pinf->bank, pinf->col);
492 if (!priv->p_data->quirks) {
493 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
494 "DDR ECC error type :%s Row %d Bank %d Col %d ",
495 "UE", pinf->row, pinf->bank, pinf->col);
496 } else {
497 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
498 "DDR ECC error type :%s Row %d Bank %d Col %d ",
499 "UE", pinf->row, pinf->bank, pinf->col);
500 snprintf(priv->message, SYNPS_EDAC_MSG_SIZE,
501 "BankGroup Number %d Block Number %d",
502 pinf->bankgrpnr, pinf->blknr);
503 }
504
414 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
415 p->ue_cnt, 0, 0, 0, 0, 0, -1,
416 priv->message, "");
417 }
418
419 memset(p, 0, sizeof(*p));
420}
421
422/**
505 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci,
506 p->ue_cnt, 0, 0, 0, 0, 0, -1,
507 priv->message, "");
508 }
509
510 memset(p, 0, sizeof(*p));
511}
512
513/**
514 * intr_handler - Interrupt Handler for ECC interrupts.
515 * @irq: IRQ number.
516 * @dev_id: Device ID.
517 *
518 * Return: IRQ_NONE, if interrupt not set or IRQ_HANDLED otherwise.
519 */
520static irqreturn_t intr_handler(int irq, void *dev_id)
521{
522 const struct synps_platform_data *p_data;
523 struct mem_ctl_info *mci = dev_id;
524 struct synps_edac_priv *priv;
525 int status, regval;
526
527 priv = mci->pvt_info;
528 p_data = priv->p_data;
529
530 regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
531 regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK);
532 if (!(regval & ECC_CE_UE_INTR_MASK))
533 return IRQ_NONE;
534
535 status = p_data->get_error_info(priv);
536 if (status)
537 return IRQ_NONE;
538
539 priv->ce_cnt += priv->stat.ce_cnt;
540 priv->ue_cnt += priv->stat.ue_cnt;
541 handle_error(mci, &priv->stat);
542
543 edac_dbg(3, "Total error count CE %d UE %d\n",
544 priv->ce_cnt, priv->ue_cnt);
545 writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
546 return IRQ_HANDLED;
547}
548
549/**
423 * check_errors - Check controller for ECC errors.
424 * @mci: EDAC memory controller instance.
425 *
426 * Check and post ECC errors. Called by the polling thread.
427 */
428static void check_errors(struct mem_ctl_info *mci)
429{
550 * check_errors - Check controller for ECC errors.
551 * @mci: EDAC memory controller instance.
552 *
553 * Check and post ECC errors. Called by the polling thread.
554 */
555static void check_errors(struct mem_ctl_info *mci)
556{
430 struct synps_edac_priv *priv = mci->pvt_info;
431 const struct synps_platform_data *p_data = priv->p_data;
557 const struct synps_platform_data *p_data;
558 struct synps_edac_priv *priv;
432 int status;
433
559 int status;
560
561 priv = mci->pvt_info;
562 p_data = priv->p_data;
563
434 status = p_data->get_error_info(priv);
435 if (status)
436 return;
437
438 priv->ce_cnt += priv->stat.ce_cnt;
439 priv->ue_cnt += priv->stat.ue_cnt;
440 handle_error(mci, &priv->stat);
441

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470 default:
471 dt = DEV_UNKNOWN;
472 }
473
474 return dt;
475}
476
477/**
564 status = p_data->get_error_info(priv);
565 if (status)
566 return;
567
568 priv->ce_cnt += priv->stat.ce_cnt;
569 priv->ue_cnt += priv->stat.ue_cnt;
570 handle_error(mci, &priv->stat);
571

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600 default:
601 dt = DEV_UNKNOWN;
602 }
603
604 return dt;
605}
606
607/**
608 * zynqmp_get_dtype - Return the controller memory width.
609 * @base: DDR memory controller base address.
610 *
611 * Get the EDAC device type width appropriate for the current controller
612 * configuration.
613 *
614 * Return: a device type width enumeration.
615 */
616static enum dev_type zynqmp_get_dtype(const void __iomem *base)
617{
618 enum dev_type dt;
619 u32 width;
620
621 width = readl(base + CTRL_OFST);
622 width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT;
623 switch (width) {
624 case DDRCTL_EWDTH_16:
625 dt = DEV_X2;
626 break;
627 case DDRCTL_EWDTH_32:
628 dt = DEV_X4;
629 break;
630 case DDRCTL_EWDTH_64:
631 dt = DEV_X8;
632 break;
633 default:
634 dt = DEV_UNKNOWN;
635 }
636
637 return dt;
638}
639
640/**
478 * zynq_get_ecc_state - Return the controller ECC enable/disable status.
479 * @base: DDR memory controller base address.
480 *
481 * Get the ECC enable/disable status of the controller.
482 *
483 * Return: true if enabled, otherwise false.
484 */
485static bool zynq_get_ecc_state(void __iomem *base)
486{
641 * zynq_get_ecc_state - Return the controller ECC enable/disable status.
642 * @base: DDR memory controller base address.
643 *
644 * Get the ECC enable/disable status of the controller.
645 *
646 * Return: true if enabled, otherwise false.
647 */
648static bool zynq_get_ecc_state(void __iomem *base)
649{
487 bool state = false;
488 enum dev_type dt;
489 u32 ecctype;
490
491 dt = zynq_get_dtype(base);
492 if (dt == DEV_UNKNOWN)
650 enum dev_type dt;
651 u32 ecctype;
652
653 dt = zynq_get_dtype(base);
654 if (dt == DEV_UNKNOWN)
493 return state;
655 return false;
494
495 ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK;
496 if ((ecctype == SCRUB_MODE_SECDED) && (dt == DEV_X2))
656
657 ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK;
658 if ((ecctype == SCRUB_MODE_SECDED) && (dt == DEV_X2))
497 state = true;
659 return true;
498
660
499 return state;
661 return false;
500}
501
502/**
662}
663
664/**
665 * zynqmp_get_ecc_state - Return the controller ECC enable/disable status.
666 * @base: DDR memory controller base address.
667 *
668 * Get the ECC enable/disable status for the controller.
669 *
670 * Return: a ECC status boolean i.e true/false - enabled/disabled.
671 */
672static bool zynqmp_get_ecc_state(void __iomem *base)
673{
674 enum dev_type dt;
675 u32 ecctype;
676
677 dt = zynqmp_get_dtype(base);
678 if (dt == DEV_UNKNOWN)
679 return false;
680
681 ecctype = readl(base + ECC_CFG0_OFST) & SCRUB_MODE_MASK;
682 if ((ecctype == SCRUB_MODE_SECDED) &&
683 ((dt == DEV_X2) || (dt == DEV_X4) || (dt == DEV_X8)))
684 return true;
685
686 return false;
687}
688
689/**
503 * get_memsize - Read the size of the attached memory device.
504 *
505 * Return: the memory size in bytes.
506 */
507static u32 get_memsize(void)
508{
509 struct sysinfo inf;
510

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533 mt = MEM_DDR3;
534 else
535 mt = MEM_DDR2;
536
537 return mt;
538}
539
540/**
690 * get_memsize - Read the size of the attached memory device.
691 *
692 * Return: the memory size in bytes.
693 */
694static u32 get_memsize(void)
695{
696 struct sysinfo inf;
697

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720 mt = MEM_DDR3;
721 else
722 mt = MEM_DDR2;
723
724 return mt;
725}
726
727/**
728 * zynqmp_get_mtype - Returns controller memory type.
729 * @base: Synopsys ECC status structure.
730 *
731 * Get the EDAC memory type appropriate for the current controller
732 * configuration.
733 *
734 * Return: a memory type enumeration.
735 */
736static enum mem_type zynqmp_get_mtype(const void __iomem *base)
737{
738 enum mem_type mt;
739 u32 memtype;
740
741 memtype = readl(base + CTRL_OFST);
742
743 if ((memtype & MEM_TYPE_DDR3) || (memtype & MEM_TYPE_LPDDR3))
744 mt = MEM_DDR3;
745 else if (memtype & MEM_TYPE_DDR2)
746 mt = MEM_RDDR2;
747 else if ((memtype & MEM_TYPE_LPDDR4) || (memtype & MEM_TYPE_DDR4))
748 mt = MEM_DDR4;
749 else
750 mt = MEM_EMPTY;
751
752 return mt;
753}
754
755/**
541 * init_csrows - Initialize the csrow data.
542 * @mci: EDAC memory controller instance.
543 *
544 * Initialize the chip select rows associated with the EDAC memory
545 * controller instance.
546 */
547static void init_csrows(struct mem_ctl_info *mci)
548{

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593 mci->scrub_cap = SCRUB_HW_SRC;
594 mci->scrub_mode = SCRUB_NONE;
595
596 mci->edac_cap = EDAC_FLAG_SECDED;
597 mci->ctl_name = "synps_ddr_controller";
598 mci->dev_name = SYNPS_EDAC_MOD_STRING;
599 mci->mod_name = SYNPS_EDAC_MOD_VER;
600
756 * init_csrows - Initialize the csrow data.
757 * @mci: EDAC memory controller instance.
758 *
759 * Initialize the chip select rows associated with the EDAC memory
760 * controller instance.
761 */
762static void init_csrows(struct mem_ctl_info *mci)
763{

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808 mci->scrub_cap = SCRUB_HW_SRC;
809 mci->scrub_mode = SCRUB_NONE;
810
811 mci->edac_cap = EDAC_FLAG_SECDED;
812 mci->ctl_name = "synps_ddr_controller";
813 mci->dev_name = SYNPS_EDAC_MOD_STRING;
814 mci->mod_name = SYNPS_EDAC_MOD_VER;
815
601 edac_op_state = EDAC_OPSTATE_POLL;
602 mci->edac_check = check_errors;
816 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
817 edac_op_state = EDAC_OPSTATE_INT;
818 } else {
819 edac_op_state = EDAC_OPSTATE_POLL;
820 mci->edac_check = check_errors;
821 }
822
603 mci->ctl_page_to_phys = NULL;
604
605 init_csrows(mci);
606}
607
823 mci->ctl_page_to_phys = NULL;
824
825 init_csrows(mci);
826}
827
828static void enable_intr(struct synps_edac_priv *priv)
829{
830 /* Enable UE/CE Interrupts */
831 writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
832 priv->baseaddr + DDR_QOS_IRQ_EN_OFST);
833}
834
835static void disable_intr(struct synps_edac_priv *priv)
836{
837 /* Disable UE/CE Interrupts */
838 writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
839 priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
840}
841
842static int setup_irq(struct mem_ctl_info *mci,
843 struct platform_device *pdev)
844{
845 struct synps_edac_priv *priv = mci->pvt_info;
846 int ret, irq;
847
848 irq = platform_get_irq(pdev, 0);
849 if (irq < 0) {
850 edac_printk(KERN_ERR, EDAC_MC,
851 "No IRQ %d in DT\n", irq);
852 return irq;
853 }
854
855 ret = devm_request_irq(&pdev->dev, irq, intr_handler,
856 0, dev_name(&pdev->dev), mci);
857 if (ret < 0) {
858 edac_printk(KERN_ERR, EDAC_MC, "Failed to request IRQ\n");
859 return ret;
860 }
861
862 enable_intr(priv);
863
864 return 0;
865}
866
608static const struct synps_platform_data zynq_edac_def = {
609 .get_error_info = zynq_get_error_info,
610 .get_mtype = zynq_get_mtype,
611 .get_dtype = zynq_get_dtype,
612 .get_ecc_state = zynq_get_ecc_state,
613 .quirks = 0,
614};
615
867static const struct synps_platform_data zynq_edac_def = {
868 .get_error_info = zynq_get_error_info,
869 .get_mtype = zynq_get_mtype,
870 .get_dtype = zynq_get_dtype,
871 .get_ecc_state = zynq_get_ecc_state,
872 .quirks = 0,
873};
874
875static const struct synps_platform_data zynqmp_edac_def = {
876 .get_error_info = zynqmp_get_error_info,
877 .get_mtype = zynqmp_get_mtype,
878 .get_dtype = zynqmp_get_dtype,
879 .get_ecc_state = zynqmp_get_ecc_state,
880 .quirks = DDR_ECC_INTR_SUPPORT,
881};
882
616static const struct of_device_id synps_edac_match[] = {
883static const struct of_device_id synps_edac_match[] = {
617 { .compatible = "xlnx,zynq-ddrc-a05", .data = (void *)&zynq_edac_def },
618 { /* end of table */ }
884 {
885 .compatible = "xlnx,zynq-ddrc-a05",
886 .data = (void *)&zynq_edac_def
887 },
888 {
889 .compatible = "xlnx,zynqmp-ddrc-2.40a",
890 .data = (void *)&zynqmp_edac_def
891 },
892 {
893 /* end of table */
894 }
619};
620
621MODULE_DEVICE_TABLE(of, synps_edac_match);
622
623/**
624 * mc_probe - Check controller and bind driver.
625 * @pdev: platform device.
626 *

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669 }
670
671 priv = mci->pvt_info;
672 priv->baseaddr = baseaddr;
673 priv->p_data = p_data;
674
675 mc_init(mci, pdev);
676
895};
896
897MODULE_DEVICE_TABLE(of, synps_edac_match);
898
899/**
900 * mc_probe - Check controller and bind driver.
901 * @pdev: platform device.
902 *

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945 }
946
947 priv = mci->pvt_info;
948 priv->baseaddr = baseaddr;
949 priv->p_data = p_data;
950
951 mc_init(mci, pdev);
952
953 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) {
954 rc = setup_irq(mci, pdev);
955 if (rc)
956 goto free_edac_mc;
957 }
958
677 rc = edac_mc_add_mc(mci);
678 if (rc) {
679 edac_printk(KERN_ERR, EDAC_MC,
680 "Failed to register with EDAC core\n");
681 goto free_edac_mc;
682 }
683
684 /*
685 * Start capturing the correctable and uncorrectable errors. A write of
686 * 0 starts the counters.
687 */
959 rc = edac_mc_add_mc(mci);
960 if (rc) {
961 edac_printk(KERN_ERR, EDAC_MC,
962 "Failed to register with EDAC core\n");
963 goto free_edac_mc;
964 }
965
966 /*
967 * Start capturing the correctable and uncorrectable errors. A write of
968 * 0 starts the counters.
969 */
688 writel(0x0, baseaddr + ECC_CTRL_OFST);
970 if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT))
971 writel(0x0, baseaddr + ECC_CTRL_OFST);
972
689 return rc;
690
691free_edac_mc:
692 edac_mc_free(mci);
693
694 return rc;
695}
696
697/**
698 * mc_remove - Unbind driver from controller.
699 * @pdev: Platform device.
700 *
701 * Return: Unconditionally 0
702 */
703static int mc_remove(struct platform_device *pdev)
704{
705 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
973 return rc;
974
975free_edac_mc:
976 edac_mc_free(mci);
977
978 return rc;
979}
980
981/**
982 * mc_remove - Unbind driver from controller.
983 * @pdev: Platform device.
984 *
985 * Return: Unconditionally 0
986 */
987static int mc_remove(struct platform_device *pdev)
988{
989 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
990 struct synps_edac_priv *priv = mci->pvt_info;
706
991
992 if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)
993 disable_intr(priv);
994
707 edac_mc_del_mc(&pdev->dev);
708 edac_mc_free(mci);
709
710 return 0;
711}
712
713static struct platform_driver synps_edac_mc_driver = {
714 .driver = {

--- 12 unchanged lines hidden --- 		995 edac_mc_del_mc(&pdev->dev);
996 edac_mc_free(mci);
997
998 return 0;
999}
1000
1001static struct platform_driver synps_edac_mc_driver = {
1002 .driver = {

--- 12 unchanged lines hidden ---