sb_edac.c (a7d7d2e1a07e3811dc49af2962c940fd8bbb6c8f) sb_edac.c (084a4fccef39ac7abb039511f32380f28d0b67e6)
1/* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
2 *
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
5 *
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
8 *

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546 }
547
548 debugf0("Number of active channels: %d, number of active dimms: %d\n",
549 *channels, *csrows);
550
551 return 0;
552}
553
1/* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
2 *
3 * This driver supports the memory controllers found on the Intel
4 * processor family Sandy Bridge.
5 *
6 * This file may be distributed under the terms of the
7 * GNU General Public License version 2 only.
8 *

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546 }
547
548 debugf0("Number of active channels: %d, number of active dimms: %d\n",
549 *channels, *csrows);
550
551 return 0;
552}
553
554static int get_dimm_config(const struct mem_ctl_info *mci)
554static int get_dimm_config(struct mem_ctl_info *mci)
555{
556 struct sbridge_pvt *pvt = mci->pvt_info;
557 struct csrow_info *csr;
558 int i, j, banks, ranks, rows, cols, size, npages;
559 int csrow = 0;
560 unsigned long last_page = 0;
561 u32 reg;
562 enum edac_type mode;
563 enum mem_type mtype;
555{
556 struct sbridge_pvt *pvt = mci->pvt_info;
557 struct csrow_info *csr;
558 int i, j, banks, ranks, rows, cols, size, npages;
559 int csrow = 0;
560 unsigned long last_page = 0;
561 u32 reg;
562 enum edac_type mode;
563 enum mem_type mtype;
564 struct dimm_info *dimm;
564
565 pci_read_config_dword(pvt->pci_br, SAD_TARGET, &reg);
566 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
567
568 pci_read_config_dword(pvt->pci_br, SAD_CONTROL, &reg);
569 pvt->sbridge_dev->node_id = NODE_ID(reg);
570 debugf0("mc#%d: Node ID: %d, source ID: %d\n",
571 pvt->sbridge_dev->mc,

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607 } else {
608 debugf0("Memory is unregistered\n");
609 mtype = MEM_DDR3;
610 }
611
612 /* On all supported DDR3 DIMM types, there are 8 banks available */
613 banks = 8;
614
565
566 pci_read_config_dword(pvt->pci_br, SAD_TARGET, &reg);
567 pvt->sbridge_dev->source_id = SOURCE_ID(reg);
568
569 pci_read_config_dword(pvt->pci_br, SAD_CONTROL, &reg);
570 pvt->sbridge_dev->node_id = NODE_ID(reg);
571 debugf0("mc#%d: Node ID: %d, source ID: %d\n",
572 pvt->sbridge_dev->mc,

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608 } else {
609 debugf0("Memory is unregistered\n");
610 mtype = MEM_DDR3;
611 }
612
613 /* On all supported DDR3 DIMM types, there are 8 banks available */
614 banks = 8;
615
616 dimm = mci->dimms;
615 for (i = 0; i < NUM_CHANNELS; i++) {
616 u32 mtr;
617
618 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
619 pci_read_config_dword(pvt->pci_tad[i],
620 mtr_regs[j], &mtr);
621 debugf4("Channel #%d MTR%d = %x\n", i, j, mtr);
622 if (IS_DIMM_PRESENT(mtr)) {

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629 /* DDR3 has 8 I/O banks */
630 size = (rows * cols * banks * ranks) >> (20 - 3);
631 npages = MiB_TO_PAGES(size);
632
633 debugf0("mc#%d: channel %d, dimm %d, %d Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
634 pvt->sbridge_dev->mc, i, j,
635 size, npages,
636 banks, ranks, rows, cols);
617 for (i = 0; i < NUM_CHANNELS; i++) {
618 u32 mtr;
619
620 for (j = 0; j < ARRAY_SIZE(mtr_regs); j++) {
621 pci_read_config_dword(pvt->pci_tad[i],
622 mtr_regs[j], &mtr);
623 debugf4("Channel #%d MTR%d = %x\n", i, j, mtr);
624 if (IS_DIMM_PRESENT(mtr)) {

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631 /* DDR3 has 8 I/O banks */
632 size = (rows * cols * banks * ranks) >> (20 - 3);
633 npages = MiB_TO_PAGES(size);
634
635 debugf0("mc#%d: channel %d, dimm %d, %d Mb (%d pages) bank: %d, rank: %d, row: %#x, col: %#x\n",
636 pvt->sbridge_dev->mc, i, j,
637 size, npages,
638 banks, ranks, rows, cols);
637 csr = &mci->csrows[csrow];
638
639
640 /*
641 * Fake stuff. This controller doesn't see
642 * csrows.
643 */
644 csr = &mci->csrows[csrow];
639 csr->first_page = last_page;
640 csr->last_page = last_page + npages - 1;
645 csr->first_page = last_page;
646 csr->last_page = last_page + npages - 1;
641 csr->page_mask = 0UL; /* Unused */
642 csr->nr_pages = npages;
647 csr->nr_pages = npages;
643 csr->grain = 32;
644 csr->csrow_idx = csrow;
648 csr->csrow_idx = csrow;
645 csr->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
646 csr->ce_count = 0;
647 csr->ue_count = 0;
648 csr->mtype = mtype;
649 csr->edac_mode = mode;
650 csr->nr_channels = 1;
651 csr->channels[0].chan_idx = i;
649 csr->nr_channels = 1;
650 csr->channels[0].chan_idx = i;
652 csr->channels[0].ce_count = 0;
653 pvt->csrow_map[i][j] = csrow;
651 pvt->csrow_map[i][j] = csrow;
654 snprintf(csr->channels[0].dimm->label,
655 sizeof(csr->channels[0].dimm->label),
656 "CPU_SrcID#%u_Channel#%u_DIMM#%u",
657 pvt->sbridge_dev->source_id, i, j);
658 last_page += npages;
659 csrow++;
652 last_page += npages;
653 csrow++;
654
655 csr->channels[0].dimm = dimm;
656 dimm->grain = 32;
657 dimm->dtype = (banks == 8) ? DEV_X8 : DEV_X4;
658 dimm->mtype = mtype;
659 dimm->edac_mode = mode;
660 snprintf(dimm->label, sizeof(dimm->label),
661 "CPU_SrcID#%u_Channel#%u_DIMM#%u",
662 pvt->sbridge_dev->source_id, i, j);
660 }
661 }
662 }
663
664 return 0;
665}
666
667static void get_memory_layout(const struct mem_ctl_info *mci)

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664 }
665 }
666
667 return 0;
668}
669
670static void get_memory_layout(const struct mem_ctl_info *mci)

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