i82975x_edac.c (a7d7d2e1a07e3811dc49af2962c940fd8bbb6c8f) i82975x_edac.c (084a4fccef39ac7abb039511f32380f28d0b67e6)
1/*
2 * Intel 82975X Memory Controller kernel module
3 * (C) 2007 aCarLab (India) Pvt. Ltd. (http://acarlab.com)
4 * (C) 2007 jetzbroadband (http://jetzbroadband.com)
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
8 * Written by Arvind R.

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304 "\t EAP=0x%08x\n"
305 "\tPAGE=0x%08x\n",
306 (info->xeap & 1) ? 1 : 0, info->eap, (unsigned int) page);
307 return 0;
308 }
309 chan = (mci->csrows[row].nr_channels == 1) ? 0 : info->eap & 1;
310 offst = info->eap
311 & ((1 << PAGE_SHIFT) -
1/*
2 * Intel 82975X Memory Controller kernel module
3 * (C) 2007 aCarLab (India) Pvt. Ltd. (http://acarlab.com)
4 * (C) 2007 jetzbroadband (http://jetzbroadband.com)
5 * This file may be distributed under the terms of the
6 * GNU General Public License.
7 *
8 * Written by Arvind R.

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304 "\t EAP=0x%08x\n"
305 "\tPAGE=0x%08x\n",
306 (info->xeap & 1) ? 1 : 0, info->eap, (unsigned int) page);
307 return 0;
308 }
309 chan = (mci->csrows[row].nr_channels == 1) ? 0 : info->eap & 1;
310 offst = info->eap
311 & ((1 << PAGE_SHIFT) -
312 (1 << mci->csrows[row].grain));
312 (1 << mci->csrows[row].channels[chan].dimm->grain));
313
314 if (info->errsts & 0x0002)
315 edac_mc_handle_ue(mci, page, offst , row, "i82975x UE");
316 else
317 edac_mc_handle_ce(mci, page, offst, info->derrsyn, row,
318 chan, "i82975x CE");
319
320 return 1;

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367 "DIMM A1", "DIMM A2",
368 "DIMM B1", "DIMM B2"
369 };
370 struct csrow_info *csrow;
371 unsigned long last_cumul_size;
372 u8 value;
373 u32 cumul_size;
374 int index, chan;
313
314 if (info->errsts & 0x0002)
315 edac_mc_handle_ue(mci, page, offst , row, "i82975x UE");
316 else
317 edac_mc_handle_ce(mci, page, offst, info->derrsyn, row,
318 chan, "i82975x CE");
319
320 return 1;

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367 "DIMM A1", "DIMM A2",
368 "DIMM B1", "DIMM B2"
369 };
370 struct csrow_info *csrow;
371 unsigned long last_cumul_size;
372 u8 value;
373 u32 cumul_size;
374 int index, chan;
375 struct dimm_info *dimm;
376 enum dev_type dtype;
375
376 last_cumul_size = 0;
377
378 /*
379 * 82875 comment:
380 * The dram row boundary (DRB) reg values are boundary address
381 * for each DRAM row with a granularity of 32 or 64MB (single/dual
382 * channel operation). DRB regs are cumulative; therefore DRB7 will

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401 cumul_size);
402
403 /*
404 * Initialise dram labels
405 * index values:
406 * [0-7] for single-channel; i.e. csrow->nr_channels = 1
407 * [0-3] for dual-channel; i.e. csrow->nr_channels = 2
408 */
377
378 last_cumul_size = 0;
379
380 /*
381 * 82875 comment:
382 * The dram row boundary (DRB) reg values are boundary address
383 * for each DRAM row with a granularity of 32 or 64MB (single/dual
384 * channel operation). DRB regs are cumulative; therefore DRB7 will

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403 cumul_size);
404
405 /*
406 * Initialise dram labels
407 * index values:
408 * [0-7] for single-channel; i.e. csrow->nr_channels = 1
409 * [0-3] for dual-channel; i.e. csrow->nr_channels = 2
410 */
409 for (chan = 0; chan < csrow->nr_channels; chan++)
411 dtype = i82975x_dram_type(mch_window, index);
412 for (chan = 0; chan < csrow->nr_channels; chan++) {
413 dimm = mci->csrows[index].channels[chan].dimm;
410 strncpy(csrow->channels[chan].dimm->label,
411 labels[(index >> 1) + (chan * 2)],
412 EDAC_MC_LABEL_LEN);
414 strncpy(csrow->channels[chan].dimm->label,
415 labels[(index >> 1) + (chan * 2)],
416 EDAC_MC_LABEL_LEN);
417 dimm->grain = 1 << 7; /* 128Byte cache-line resolution */
418 dimm->dtype = i82975x_dram_type(mch_window, index);
419 dimm->mtype = MEM_DDR2; /* I82975x supports only DDR2 */
420 dimm->edac_mode = EDAC_SECDED; /* only supported */
421 }
413
414 if (cumul_size == last_cumul_size)
415 continue; /* not populated */
416
417 csrow->first_page = last_cumul_size;
418 csrow->last_page = cumul_size - 1;
419 csrow->nr_pages = cumul_size - last_cumul_size;
420 last_cumul_size = cumul_size;
422
423 if (cumul_size == last_cumul_size)
424 continue; /* not populated */
425
426 csrow->first_page = last_cumul_size;
427 csrow->last_page = cumul_size - 1;
428 csrow->nr_pages = cumul_size - last_cumul_size;
429 last_cumul_size = cumul_size;
421 csrow->grain = 1 << 7; /* 128Byte cache-line resolution */
422 csrow->mtype = MEM_DDR2; /* I82975x supports only DDR2 */
423 csrow->dtype = i82975x_dram_type(mch_window, index);
424 csrow->edac_mode = EDAC_SECDED; /* only supported */
425 }
426}
427
428/* #define i82975x_DEBUG_IOMEM */
429
430#ifdef i82975x_DEBUG_IOMEM
431static void i82975x_print_dram_timings(void __iomem *mch_window)
432{

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431}
432
433/* #define i82975x_DEBUG_IOMEM */
434
435#ifdef i82975x_DEBUG_IOMEM
436static void i82975x_print_dram_timings(void __iomem *mch_window)
437{

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