i82875p_edac.c (e644dae645e167d154c0526358940986682a72b0) i82875p_edac.c (084a4fccef39ac7abb039511f32380f28d0b67e6)
1/*
2 * Intel D82875P Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Thayne Harbaugh
8 * Contributors:

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337 return (drc >> 21) & 0x1;
338}
339
340static void i82875p_init_csrows(struct mem_ctl_info *mci,
341 struct pci_dev *pdev,
342 void __iomem * ovrfl_window, u32 drc)
343{
344 struct csrow_info *csrow;
1/*
2 * Intel D82875P Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Thayne Harbaugh
8 * Contributors:

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337 return (drc >> 21) & 0x1;
338}
339
340static void i82875p_init_csrows(struct mem_ctl_info *mci,
341 struct pci_dev *pdev,
342 void __iomem * ovrfl_window, u32 drc)
343{
344 struct csrow_info *csrow;
345 struct dimm_info *dimm;
346 unsigned nr_chans = dual_channel_active(drc) + 1;
345 unsigned long last_cumul_size;
346 u8 value;
347 u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
348 u32 cumul_size;
347 unsigned long last_cumul_size;
348 u8 value;
349 u32 drc_ddim; /* DRAM Data Integrity Mode 0=none,2=edac */
350 u32 cumul_size;
349 int index;
351 int index, j;
350
351 drc_ddim = (drc >> 18) & 0x1;
352 last_cumul_size = 0;
353
354 /* The dram row boundary (DRB) reg values are boundary address
355 * for each DRAM row with a granularity of 32 or 64MB (single/dual
356 * channel operation). DRB regs are cumulative; therefore DRB7 will
357 * contain the total memory contained in all eight rows.

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366 cumul_size);
367 if (cumul_size == last_cumul_size)
368 continue; /* not populated */
369
370 csrow->first_page = last_cumul_size;
371 csrow->last_page = cumul_size - 1;
372 csrow->nr_pages = cumul_size - last_cumul_size;
373 last_cumul_size = cumul_size;
352
353 drc_ddim = (drc >> 18) & 0x1;
354 last_cumul_size = 0;
355
356 /* The dram row boundary (DRB) reg values are boundary address
357 * for each DRAM row with a granularity of 32 or 64MB (single/dual
358 * channel operation). DRB regs are cumulative; therefore DRB7 will
359 * contain the total memory contained in all eight rows.

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368 cumul_size);
369 if (cumul_size == last_cumul_size)
370 continue; /* not populated */
371
372 csrow->first_page = last_cumul_size;
373 csrow->last_page = cumul_size - 1;
374 csrow->nr_pages = cumul_size - last_cumul_size;
375 last_cumul_size = cumul_size;
374 csrow->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
375 csrow->mtype = MEM_DDR;
376 csrow->dtype = DEV_UNKNOWN;
377 csrow->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
376
377 for (j = 0; j < nr_chans; j++) {
378 dimm = csrow->channels[j].dimm;
379
380 dimm->grain = 1 << 12; /* I82875P_EAP has 4KiB reolution */
381 dimm->mtype = MEM_DDR;
382 dimm->dtype = DEV_UNKNOWN;
383 dimm->edac_mode = drc_ddim ? EDAC_SECDED : EDAC_NONE;
384 }
378 }
379}
380
381static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
382{
383 int rc = -ENODEV;
384 struct mem_ctl_info *mci;
385 struct i82875p_pvt *pvt;

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386}
387
388static int i82875p_probe1(struct pci_dev *pdev, int dev_idx)
389{
390 int rc = -ENODEV;
391 struct mem_ctl_info *mci;
392 struct i82875p_pvt *pvt;

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