i82860_edac.c (e644dae645e167d154c0526358940986682a72b0) i82860_edac.c (084a4fccef39ac7abb039511f32380f28d0b67e6)
1/*
2 * Intel 82860 Memory Controller kernel module
3 * (C) 2005 Red Hat (http://www.redhat.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Ben Woodard <woodard@redhat.com>
8 * shamelessly copied from and based upon the edac_i82875 driver

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135
136static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
137{
138 unsigned long last_cumul_size;
139 u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
140 u16 value;
141 u32 cumul_size;
142 struct csrow_info *csrow;
1/*
2 * Intel 82860 Memory Controller kernel module
3 * (C) 2005 Red Hat (http://www.redhat.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Ben Woodard <woodard@redhat.com>
8 * shamelessly copied from and based upon the edac_i82875 driver

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135
136static void i82860_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev)
137{
138 unsigned long last_cumul_size;
139 u16 mchcfg_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
140 u16 value;
141 u32 cumul_size;
142 struct csrow_info *csrow;
143 struct dimm_info *dimm;
143 int index;
144
145 pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
146 mchcfg_ddim = mchcfg_ddim & 0x180;
147 last_cumul_size = 0;
148
149 /* The group row boundary (GRA) reg values are boundary address
150 * for each DRAM row with a granularity of 16MB. GRA regs are
151 * cumulative; therefore GRA15 will contain the total memory contained
152 * in all eight rows.
153 */
154 for (index = 0; index < mci->nr_csrows; index++) {
155 csrow = &mci->csrows[index];
144 int index;
145
146 pci_read_config_word(pdev, I82860_MCHCFG, &mchcfg_ddim);
147 mchcfg_ddim = mchcfg_ddim & 0x180;
148 last_cumul_size = 0;
149
150 /* The group row boundary (GRA) reg values are boundary address
151 * for each DRAM row with a granularity of 16MB. GRA regs are
152 * cumulative; therefore GRA15 will contain the total memory contained
153 * in all eight rows.
154 */
155 for (index = 0; index < mci->nr_csrows; index++) {
156 csrow = &mci->csrows[index];
157 dimm = csrow->channels[0].dimm;
158
156 pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
157 cumul_size = (value & I82860_GBA_MASK) <<
158 (I82860_GBA_SHIFT - PAGE_SHIFT);
159 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
160 cumul_size);
161
162 if (cumul_size == last_cumul_size)
163 continue; /* not populated */
164
165 csrow->first_page = last_cumul_size;
166 csrow->last_page = cumul_size - 1;
167 csrow->nr_pages = cumul_size - last_cumul_size;
168 last_cumul_size = cumul_size;
159 pci_read_config_word(pdev, I82860_GBA + index * 2, &value);
160 cumul_size = (value & I82860_GBA_MASK) <<
161 (I82860_GBA_SHIFT - PAGE_SHIFT);
162 debugf3("%s(): (%d) cumul_size 0x%x\n", __func__, index,
163 cumul_size);
164
165 if (cumul_size == last_cumul_size)
166 continue; /* not populated */
167
168 csrow->first_page = last_cumul_size;
169 csrow->last_page = cumul_size - 1;
170 csrow->nr_pages = cumul_size - last_cumul_size;
171 last_cumul_size = cumul_size;
169 csrow->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */
170 csrow->mtype = MEM_RMBS;
171 csrow->dtype = DEV_UNKNOWN;
172 csrow->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
172 dimm->grain = 1 << 12; /* I82860_EAP has 4KiB reolution */
173 dimm->mtype = MEM_RMBS;
174 dimm->dtype = DEV_UNKNOWN;
175 dimm->edac_mode = mchcfg_ddim ? EDAC_SECDED : EDAC_NONE;
173 }
174}
175
176static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
177{
178 struct mem_ctl_info *mci;
179 struct i82860_error_info discard;
180

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177}
178
179static int i82860_probe1(struct pci_dev *pdev, int dev_idx)
180{
181 struct mem_ctl_info *mci;
182 struct i82860_error_info discard;
183

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