i7300_edac.c (e644dae645e167d154c0526358940986682a72b0) i7300_edac.c (084a4fccef39ac7abb039511f32380f28d0b67e6)
1/*
2 * Intel 7300 class Memory Controllers kernel module (Clarksboro)
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License version 2 only.
6 *
7 * Copyright (c) 2010 by:
8 * Mauro Carvalho Chehab <mchehab@redhat.com>

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613 * @branch: Branch number (0 or 1)
614 * @dinfo: Pointer to DIMM info where dimm size is stored
615 * @p_csrow: Pointer to the struct csrow_info that corresponds to that element
616 */
617static int decode_mtr(struct i7300_pvt *pvt,
618 int slot, int ch, int branch,
619 struct i7300_dimm_info *dinfo,
620 struct csrow_info *p_csrow,
1/*
2 * Intel 7300 class Memory Controllers kernel module (Clarksboro)
3 *
4 * This file may be distributed under the terms of the
5 * GNU General Public License version 2 only.
6 *
7 * Copyright (c) 2010 by:
8 * Mauro Carvalho Chehab <mchehab@redhat.com>

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613 * @branch: Branch number (0 or 1)
614 * @dinfo: Pointer to DIMM info where dimm size is stored
615 * @p_csrow: Pointer to the struct csrow_info that corresponds to that element
616 */
617static int decode_mtr(struct i7300_pvt *pvt,
618 int slot, int ch, int branch,
619 struct i7300_dimm_info *dinfo,
620 struct csrow_info *p_csrow,
621 struct dimm_info *dimm,
621 u32 *nr_pages)
622{
623 int mtr, ans, addrBits, channel;
624
625 channel = to_channel(ch, branch);
626
627 mtr = pvt->mtr[slot][branch];
628 ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;

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658 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
659
660 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
661 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr) ? "double" : "single");
662 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
663 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
664 debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes);
665
622 u32 *nr_pages)
623{
624 int mtr, ans, addrBits, channel;
625
626 channel = to_channel(ch, branch);
627
628 mtr = pvt->mtr[slot][branch];
629 ans = MTR_DIMMS_PRESENT(mtr) ? 1 : 0;

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659 MTR_DIMMS_ETHROTTLE(mtr) ? "enabled" : "disabled");
660
661 debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
662 debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANKS(mtr) ? "double" : "single");
663 debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
664 debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
665 debugf2("\t\tSIZE: %d MB\n", dinfo->megabytes);
666
666 p_csrow->grain = 8;
667 p_csrow->mtype = MEM_FB_DDR2;
668 p_csrow->csrow_idx = slot;
667 p_csrow->csrow_idx = slot;
669 p_csrow->page_mask = 0;
670
671 /*
672 * The type of error detection actually depends of the
673 * mode of operation. When it is just one single memory chip, at
674 * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code.
675 * In normal or mirrored mode, it uses Lockstep mode,
676 * with the possibility of using an extended algorithm for x8 memories
677 * See datasheet Sections 7.3.6 to 7.3.8
678 */
679
668
669 /*
670 * The type of error detection actually depends of the
671 * mode of operation. When it is just one single memory chip, at
672 * socket 0, channel 0, it uses 8-byte-over-32-byte SECDED+ code.
673 * In normal or mirrored mode, it uses Lockstep mode,
674 * with the possibility of using an extended algorithm for x8 memories
675 * See datasheet Sections 7.3.6 to 7.3.8
676 */
677
678 dimm->grain = 8;
679 dimm->mtype = MEM_FB_DDR2;
680 if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
680 if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
681 p_csrow->edac_mode = EDAC_SECDED;
681 dimm->edac_mode = EDAC_SECDED;
682 debugf2("\t\tECC code is 8-byte-over-32-byte SECDED+ code\n");
683 } else {
684 debugf2("\t\tECC code is on Lockstep mode\n");
685 if (MTR_DRAM_WIDTH(mtr) == 8)
682 debugf2("\t\tECC code is 8-byte-over-32-byte SECDED+ code\n");
683 } else {
684 debugf2("\t\tECC code is on Lockstep mode\n");
685 if (MTR_DRAM_WIDTH(mtr) == 8)
686 p_csrow->edac_mode = EDAC_S8ECD8ED;
686 dimm->edac_mode = EDAC_S8ECD8ED;
687 else
687 else
688 p_csrow->edac_mode = EDAC_S4ECD4ED;
688 dimm->edac_mode = EDAC_S4ECD4ED;
689 }
690
691 /* ask what device type on this row */
692 if (MTR_DRAM_WIDTH(mtr) == 8) {
693 debugf2("\t\tScrub algorithm for x8 is on %s mode\n",
694 IS_SCRBALGO_ENHANCED(pvt->mc_settings) ?
695 "enhanced" : "normal");
696
689 }
690
691 /* ask what device type on this row */
692 if (MTR_DRAM_WIDTH(mtr) == 8) {
693 debugf2("\t\tScrub algorithm for x8 is on %s mode\n",
694 IS_SCRBALGO_ENHANCED(pvt->mc_settings) ?
695 "enhanced" : "normal");
696
697 p_csrow->dtype = DEV_X8;
697 dimm->dtype = DEV_X8;
698 } else
698 } else
699 p_csrow->dtype = DEV_X4;
699 dimm->dtype = DEV_X4;
700
701 return mtr;
702}
703
704/**
705 * print_dimm_size() - Prints dump of the memory organization
706 * @pvt: pointer to the private data struct used by i7300 driver
707 *

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774{
775 struct i7300_pvt *pvt;
776 struct i7300_dimm_info *dinfo;
777 struct csrow_info *p_csrow;
778 int rc = -ENODEV;
779 int mtr;
780 int ch, branch, slot, channel;
781 u32 last_page = 0, nr_pages;
700
701 return mtr;
702}
703
704/**
705 * print_dimm_size() - Prints dump of the memory organization
706 * @pvt: pointer to the private data struct used by i7300 driver
707 *

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774{
775 struct i7300_pvt *pvt;
776 struct i7300_dimm_info *dinfo;
777 struct csrow_info *p_csrow;
778 int rc = -ENODEV;
779 int mtr;
780 int ch, branch, slot, channel;
781 u32 last_page = 0, nr_pages;
782 struct dimm_info *dimm;
782
783 pvt = mci->pvt_info;
784
785 debugf2("Memory Technology Registers:\n");
786
787 /* Get the AMB present registers for the four channels */
788 for (branch = 0; branch < MAX_BRANCHES; branch++) {
789 /* Read and dump branch 0's MTRs */

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798 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
799 AMBPRESENT_1,
800 &pvt->ambpresent[channel]);
801 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
802 channel, pvt->ambpresent[channel]);
803 }
804
805 /* Get the set of MTR[0-7] regs by each branch */
783
784 pvt = mci->pvt_info;
785
786 debugf2("Memory Technology Registers:\n");
787
788 /* Get the AMB present registers for the four channels */
789 for (branch = 0; branch < MAX_BRANCHES; branch++) {
790 /* Read and dump branch 0's MTRs */

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799 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
800 AMBPRESENT_1,
801 &pvt->ambpresent[channel]);
802 debugf2("\t\tAMB-present CH%d = 0x%x:\n",
803 channel, pvt->ambpresent[channel]);
804 }
805
806 /* Get the set of MTR[0-7] regs by each branch */
807 nr_pages = 0;
806 for (slot = 0; slot < MAX_SLOTS; slot++) {
807 int where = mtr_regs[slot];
808 for (branch = 0; branch < MAX_BRANCHES; branch++) {
809 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
810 where,
811 &pvt->mtr[slot][branch]);
808 for (slot = 0; slot < MAX_SLOTS; slot++) {
809 int where = mtr_regs[slot];
810 for (branch = 0; branch < MAX_BRANCHES; branch++) {
811 pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
812 where,
813 &pvt->mtr[slot][branch]);
812 for (ch = 0; ch < MAX_BRANCHES; ch++) {
814 for (ch = 0; ch < MAX_CH_PER_BRANCH; ch++) {
813 int channel = to_channel(ch, branch);
814
815 dinfo = &pvt->dimm_info[slot][channel];
816 p_csrow = &mci->csrows[slot];
817
815 int channel = to_channel(ch, branch);
816
817 dinfo = &pvt->dimm_info[slot][channel];
818 p_csrow = &mci->csrows[slot];
819
820 dimm = p_csrow->channels[branch * MAX_CH_PER_BRANCH + ch].dimm;
821
818 mtr = decode_mtr(pvt, slot, ch, branch,
822 mtr = decode_mtr(pvt, slot, ch, branch,
819 dinfo, p_csrow, &nr_pages);
823 dinfo, p_csrow, dimm,
824 &nr_pages);
820 /* if no DIMMS on this row, continue */
821 if (!MTR_DIMMS_PRESENT(mtr))
822 continue;
823
824 /* Update per_csrow memory count */
825 p_csrow->nr_pages += nr_pages;
826 p_csrow->first_page = last_page;
827 last_page += nr_pages;

--- 421 unchanged lines hidden --- 		825 /* if no DIMMS on this row, continue */
826 if (!MTR_DIMMS_PRESENT(mtr))
827 continue;
828
829 /* Update per_csrow memory count */
830 p_csrow->nr_pages += nr_pages;
831 p_csrow->first_page = last_page;
832 last_page += nr_pages;

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