i3000_edac.c (e644dae645e167d154c0526358940986682a72b0) i3000_edac.c (084a4fccef39ac7abb039511f32380f28d0b67e6)
1/*
2 * Intel 3000/3010 Memory Controller kernel module
3 * Copyright (C) 2007 Akamai Technologies, Inc.
4 * Shamelessly copied from:
5 * Intel D82875P Memory Controller kernel module
6 * (C) 2003 Linux Networx (http://lnxi.com)
7 *
8 * This file may be distributed under the terms of the

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299 return 0;
300
301 return 1;
302}
303
304static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
305{
306 int rc;
1/*
2 * Intel 3000/3010 Memory Controller kernel module
3 * Copyright (C) 2007 Akamai Technologies, Inc.
4 * Shamelessly copied from:
5 * Intel D82875P Memory Controller kernel module
6 * (C) 2003 Linux Networx (http://lnxi.com)
7 *
8 * This file may be distributed under the terms of the

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299 return 0;
300
301 return 1;
302}
303
304static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
305{
306 int rc;
307 int i;
307 int i, j;
308 struct mem_ctl_info *mci = NULL;
309 unsigned long last_cumul_size;
310 int interleaved, nr_channels;
311 unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
312 unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
313 unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL];
314 unsigned long mchbar;
315 void __iomem *window;

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381 struct csrow_info *csrow = &mci->csrows[i];
382
383 value = drb[i];
384 cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
385 if (interleaved)
386 cumul_size <<= 1;
387 debugf3("MC: %s(): (%d) cumul_size 0x%x\n",
388 __func__, i, cumul_size);
308 struct mem_ctl_info *mci = NULL;
309 unsigned long last_cumul_size;
310 int interleaved, nr_channels;
311 unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
312 unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
313 unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL];
314 unsigned long mchbar;
315 void __iomem *window;

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381 struct csrow_info *csrow = &mci->csrows[i];
382
383 value = drb[i];
384 cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
385 if (interleaved)
386 cumul_size <<= 1;
387 debugf3("MC: %s(): (%d) cumul_size 0x%x\n",
388 __func__, i, cumul_size);
389 if (cumul_size == last_cumul_size) {
390 csrow->mtype = MEM_EMPTY;
389 if (cumul_size == last_cumul_size)
391 continue;
390 continue;
392 }
393
394 csrow->first_page = last_cumul_size;
395 csrow->last_page = cumul_size - 1;
396 csrow->nr_pages = cumul_size - last_cumul_size;
397 last_cumul_size = cumul_size;
391
392 csrow->first_page = last_cumul_size;
393 csrow->last_page = cumul_size - 1;
394 csrow->nr_pages = cumul_size - last_cumul_size;
395 last_cumul_size = cumul_size;
398 csrow->grain = I3000_DEAP_GRAIN;
399 csrow->mtype = MEM_DDR2;
400 csrow->dtype = DEV_UNKNOWN;
401 csrow->edac_mode = EDAC_UNKNOWN;
396
397 for (j = 0; j < nr_channels; j++) {
398 struct dimm_info *dimm = csrow->channels[j].dimm;
399 dimm->grain = I3000_DEAP_GRAIN;
400 dimm->mtype = MEM_DDR2;
401 dimm->dtype = DEV_UNKNOWN;
402 dimm->edac_mode = EDAC_UNKNOWN;
403 }
402 }
403
404 /*
405 * Clear any error bits.
406 * (Yes, we really clear bits by writing 1 to them.)
407 */
408 pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
409 I3000_ERRSTS_BITS);

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405
406 /*
407 * Clear any error bits.
408 * (Yes, we really clear bits by writing 1 to them.)
409 */
410 pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
411 I3000_ERRSTS_BITS);

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