e7xxx_edac.c (e644dae645e167d154c0526358940986682a72b0) e7xxx_edac.c (084a4fccef39ac7abb039511f32380f28d0b67e6)
1/*
2 * Intel e7xxx Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * See "enum e7xxx_chips" below for supported chipsets
8 *

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342 /* only e7501 can be single channel */
343 return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1;
344}
345
346static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
347 int dev_idx, u32 drc)
348{
349 unsigned long last_cumul_size;
1/*
2 * Intel e7xxx Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * See "enum e7xxx_chips" below for supported chipsets
8 *

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342 /* only e7501 can be single channel */
343 return (dev_idx == E7501) ? ((drc >> 18) & 0x3) : 1;
344}
345
346static void e7xxx_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
347 int dev_idx, u32 drc)
348{
349 unsigned long last_cumul_size;
350 int index;
350 int index, j;
351 u8 value;
352 u32 dra, cumul_size;
353 int drc_chan, drc_drbg, drc_ddim, mem_dev;
354 struct csrow_info *csrow;
351 u8 value;
352 u32 dra, cumul_size;
353 int drc_chan, drc_drbg, drc_ddim, mem_dev;
354 struct csrow_info *csrow;
355 struct dimm_info *dimm;
355
356 pci_read_config_dword(pdev, E7XXX_DRA, &dra);
357 drc_chan = dual_channel_active(drc, dev_idx);
358 drc_drbg = drb_granularity(drc, dev_idx);
359 drc_ddim = (drc >> 20) & 0x3;
360 last_cumul_size = 0;
361
362 /* The dram row boundary (DRB) reg values are boundary address

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376 cumul_size);
377 if (cumul_size == last_cumul_size)
378 continue; /* not populated */
379
380 csrow->first_page = last_cumul_size;
381 csrow->last_page = cumul_size - 1;
382 csrow->nr_pages = cumul_size - last_cumul_size;
383 last_cumul_size = cumul_size;
356
357 pci_read_config_dword(pdev, E7XXX_DRA, &dra);
358 drc_chan = dual_channel_active(drc, dev_idx);
359 drc_drbg = drb_granularity(drc, dev_idx);
360 drc_ddim = (drc >> 20) & 0x3;
361 last_cumul_size = 0;
362
363 /* The dram row boundary (DRB) reg values are boundary address

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377 cumul_size);
378 if (cumul_size == last_cumul_size)
379 continue; /* not populated */
380
381 csrow->first_page = last_cumul_size;
382 csrow->last_page = cumul_size - 1;
383 csrow->nr_pages = cumul_size - last_cumul_size;
384 last_cumul_size = cumul_size;
384 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
385 csrow->mtype = MEM_RDDR; /* only one type supported */
386 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
387
385
388 /*
389 * if single channel or x8 devices then SECDED
390 * if dual channel and x4 then S4ECD4ED
391 */
392 if (drc_ddim) {
393 if (drc_chan && mem_dev) {
394 csrow->edac_mode = EDAC_S4ECD4ED;
395 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
396 } else {
397 csrow->edac_mode = EDAC_SECDED;
398 mci->edac_cap |= EDAC_FLAG_SECDED;
399 }
400 } else
401 csrow->edac_mode = EDAC_NONE;
386 for (j = 0; j < drc_chan + 1; j++) {
387 dimm = csrow->channels[j].dimm;
388
389 dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */
390 dimm->mtype = MEM_RDDR; /* only one type supported */
391 dimm->dtype = mem_dev ? DEV_X4 : DEV_X8;
392
393 /*
394 * if single channel or x8 devices then SECDED
395 * if dual channel and x4 then S4ECD4ED
396 */
397 if (drc_ddim) {
398 if (drc_chan && mem_dev) {
399 dimm->edac_mode = EDAC_S4ECD4ED;
400 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
401 } else {
402 dimm->edac_mode = EDAC_SECDED;
403 mci->edac_cap |= EDAC_FLAG_SECDED;
404 }
405 } else
406 dimm->edac_mode = EDAC_NONE;
407 }
402 }
403}
404
405static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
406{
407 u16 pci_data;
408 struct mem_ctl_info *mci = NULL;
409 struct e7xxx_pvt *pvt = NULL;

--- 167 unchanged lines hidden --- 		408 }
409}
410
411static int e7xxx_probe1(struct pci_dev *pdev, int dev_idx)
412{
413 u16 pci_data;
414 struct mem_ctl_info *mci = NULL;
415 struct e7xxx_pvt *pvt = NULL;

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