e752x_edac.c (e644dae645e167d154c0526358940986682a72b0) e752x_edac.c (084a4fccef39ac7abb039511f32380f28d0b67e6)
1/*
2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * See "enum e752x_chips" below for supported chipsets
8 *

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1039 u16 ddrcsr)
1040{
1041 struct csrow_info *csrow;
1042 unsigned long last_cumul_size;
1043 int index, mem_dev, drc_chan;
1044 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */
1045 int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
1046 u8 value;
1/*
2 * Intel e752x Memory Controller kernel module
3 * (C) 2004 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * See "enum e752x_chips" below for supported chipsets
8 *

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1039 u16 ddrcsr)
1040{
1041 struct csrow_info *csrow;
1042 unsigned long last_cumul_size;
1043 int index, mem_dev, drc_chan;
1044 int drc_drbg; /* DRB granularity 0=64mb, 1=128mb */
1045 int drc_ddim; /* DRAM Data Integrity Mode 0=none, 2=edac */
1046 u8 value;
1047 u32 dra, drc, cumul_size;
1047 u32 dra, drc, cumul_size, i;
1048
1049 dra = 0;
1050 for (index = 0; index < 4; index++) {
1051 u8 dra_reg;
1052 pci_read_config_byte(pdev, E752X_DRA + index, &dra_reg);
1053 dra |= dra_reg << (index * 8);
1054 }
1055 pci_read_config_dword(pdev, E752X_DRC, &drc);
1048
1049 dra = 0;
1050 for (index = 0; index < 4; index++) {
1051 u8 dra_reg;
1052 pci_read_config_byte(pdev, E752X_DRA + index, &dra_reg);
1053 dra |= dra_reg << (index * 8);
1054 }
1055 pci_read_config_dword(pdev, E752X_DRC, &drc);
1056 drc_chan = dual_channel_active(ddrcsr);
1056 drc_chan = dual_channel_active(ddrcsr) ? 1 : 0;
1057 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */
1058 drc_ddim = (drc >> 20) & 0x3;
1059
1060 /* The dram row boundary (DRB) reg values are boundary address for
1061 * each DRAM row with a granularity of 64 or 128MB (single/dual
1062 * channel operation). DRB regs are cumulative; therefore DRB7 will
1063 * contain the total memory contained in all eight rows.
1064 */

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1075 cumul_size);
1076 if (cumul_size == last_cumul_size)
1077 continue; /* not populated */
1078
1079 csrow->first_page = last_cumul_size;
1080 csrow->last_page = cumul_size - 1;
1081 csrow->nr_pages = cumul_size - last_cumul_size;
1082 last_cumul_size = cumul_size;
1057 drc_drbg = drc_chan + 1; /* 128 in dual mode, 64 in single */
1058 drc_ddim = (drc >> 20) & 0x3;
1059
1060 /* The dram row boundary (DRB) reg values are boundary address for
1061 * each DRAM row with a granularity of 64 or 128MB (single/dual
1062 * channel operation). DRB regs are cumulative; therefore DRB7 will
1063 * contain the total memory contained in all eight rows.
1064 */

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1075 cumul_size);
1076 if (cumul_size == last_cumul_size)
1077 continue; /* not populated */
1078
1079 csrow->first_page = last_cumul_size;
1080 csrow->last_page = cumul_size - 1;
1081 csrow->nr_pages = cumul_size - last_cumul_size;
1082 last_cumul_size = cumul_size;
1083 csrow->grain = 1 << 12; /* 4KiB - resolution of CELOG */
1084 csrow->mtype = MEM_RDDR; /* only one type supported */
1085 csrow->dtype = mem_dev ? DEV_X4 : DEV_X8;
1086
1083
1087 /*
1088 * if single channel or x8 devices then SECDED
1089 * if dual channel and x4 then S4ECD4ED
1090 */
1091 if (drc_ddim) {
1092 if (drc_chan && mem_dev) {
1093 csrow->edac_mode = EDAC_S4ECD4ED;
1094 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
1095 } else {
1096 csrow->edac_mode = EDAC_SECDED;
1097 mci->edac_cap |= EDAC_FLAG_SECDED;
1098 }
1099 } else
1100 csrow->edac_mode = EDAC_NONE;
1084 for (i = 0; i < drc_chan + 1; i++) {
1085 struct dimm_info *dimm = csrow->channels[i].dimm;
1086 dimm->grain = 1 << 12; /* 4KiB - resolution of CELOG */
1087 dimm->mtype = MEM_RDDR; /* only one type supported */
1088 dimm->dtype = mem_dev ? DEV_X4 : DEV_X8;
1089
1090 /*
1091 * if single channel or x8 devices then SECDED
1092 * if dual channel and x4 then S4ECD4ED
1093 */
1094 if (drc_ddim) {
1095 if (drc_chan && mem_dev) {
1096 dimm->edac_mode = EDAC_S4ECD4ED;
1097 mci->edac_cap |= EDAC_FLAG_S4ECD4ED;
1098 } else {
1099 dimm->edac_mode = EDAC_SECDED;
1100 mci->edac_cap |= EDAC_FLAG_SECDED;
1101 }
1102 } else
1103 dimm->edac_mode = EDAC_NONE;
1104 }
1101 }
1102}
1103
1104static void e752x_init_mem_map_table(struct pci_dev *pdev,
1105 struct e752x_pvt *pvt)
1106{
1107 int index;
1108 u8 value, last, row;

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1106}
1107
1108static void e752x_init_mem_map_table(struct pci_dev *pdev,
1109 struct e752x_pvt *pvt)
1110{
1111 int index;
1112 u8 value, last, row;

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