amd76x_edac.c (e644dae645e167d154c0526358940986682a72b0) amd76x_edac.c (084a4fccef39ac7abb039511f32380f28d0b67e6)
1/*
2 * AMD 76x Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Thayne Harbaugh
8 * Based on work by Dan Hollis <goemon at anime dot net> and others.

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181 amd76x_get_error_info(mci, &info);
182 amd76x_process_error_info(mci, &info, 1);
183}
184
185static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
186 enum edac_type edac_mode)
187{
188 struct csrow_info *csrow;
1/*
2 * AMD 76x Memory Controller kernel module
3 * (C) 2003 Linux Networx (http://lnxi.com)
4 * This file may be distributed under the terms of the
5 * GNU General Public License.
6 *
7 * Written by Thayne Harbaugh
8 * Based on work by Dan Hollis <goemon at anime dot net> and others.

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181 amd76x_get_error_info(mci, &info);
182 amd76x_process_error_info(mci, &info, 1);
183}
184
185static void amd76x_init_csrows(struct mem_ctl_info *mci, struct pci_dev *pdev,
186 enum edac_type edac_mode)
187{
188 struct csrow_info *csrow;
189 struct dimm_info *dimm;
189 u32 mba, mba_base, mba_mask, dms;
190 int index;
191
192 for (index = 0; index < mci->nr_csrows; index++) {
193 csrow = &mci->csrows[index];
190 u32 mba, mba_base, mba_mask, dms;
191 int index;
192
193 for (index = 0; index < mci->nr_csrows; index++) {
194 csrow = &mci->csrows[index];
195 dimm = csrow->channels[0].dimm;
194
195 /* find the DRAM Chip Select Base address and mask */
196 pci_read_config_dword(pdev,
197 AMD76X_MEM_BASE_ADDR + (index * 4), &mba);
198
199 if (!(mba & BIT(0)))
200 continue;
201
202 mba_base = mba & 0xff800000UL;
203 mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
204 pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
205 csrow->first_page = mba_base >> PAGE_SHIFT;
206 csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
207 csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
208 csrow->page_mask = mba_mask >> PAGE_SHIFT;
196
197 /* find the DRAM Chip Select Base address and mask */
198 pci_read_config_dword(pdev,
199 AMD76X_MEM_BASE_ADDR + (index * 4), &mba);
200
201 if (!(mba & BIT(0)))
202 continue;
203
204 mba_base = mba & 0xff800000UL;
205 mba_mask = ((mba & 0xff80) << 16) | 0x7fffffUL;
206 pci_read_config_dword(pdev, AMD76X_DRAM_MODE_STATUS, &dms);
207 csrow->first_page = mba_base >> PAGE_SHIFT;
208 csrow->nr_pages = (mba_mask + 1) >> PAGE_SHIFT;
209 csrow->last_page = csrow->first_page + csrow->nr_pages - 1;
210 csrow->page_mask = mba_mask >> PAGE_SHIFT;
209 csrow->grain = csrow->nr_pages << PAGE_SHIFT;
210 csrow->mtype = MEM_RDDR;
211 csrow->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
212 csrow->edac_mode = edac_mode;
211 dimm->grain = csrow->nr_pages << PAGE_SHIFT;
212 dimm->mtype = MEM_RDDR;
213 dimm->dtype = ((dms >> index) & 0x1) ? DEV_X4 : DEV_UNKNOWN;
214 dimm->edac_mode = edac_mode;
213 }
214}
215
216/**
217 * amd76x_probe1 - Perform set up for detected device
218 * @pdev; PCI device detected
219 * @dev_idx: Device type index
220 *

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216}
217
218/**
219 * amd76x_probe1 - Perform set up for detected device
220 * @pdev; PCI device detected
221 * @dev_idx: Device type index
222 *

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